CPUARMState *env = &cpu->env;
return is_a64(env) ? env->xregs[31] : env->regs[13];
}
+
+static inline bool common_semi_has_synccache(CPUArchState *env)
+{
+ /* Ok for A64, invalid for A32/T32. */
+ return is_a64(env);
+}
#endif /* TARGET_ARM */
#ifdef TARGET_RISCV
CPURISCVState *env = &cpu->env;
return env->gpr[xSP];
}
+
+static inline bool common_semi_has_synccache(CPUArchState *env)
+{
+ return true;
+}
#endif
/*
* virtual address range. This is a nop for us since we don't
* implement caches. This is only present on A64.
*/
-#ifdef TARGET_ARM
- if (is_a64(cs->env_ptr)) {
+ if (common_semi_has_synccache(env)) {
common_semi_set_ret(cs, 0);
break;
}
-#endif
-#ifdef TARGET_RISCV
- common_semi_set_ret(cs, 0);
-#endif
- /* fall through -- invalid for A32/T32 */
+ /* fall through */
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
cpu_dump_state(cs, stderr, 0);