drm/nouveau/disp/gm200-: fix NV_PDISP_SOR_HDMI2_CTRL(n) selection

This is a SOR register, and not indexed by the bound head.

Fixes display not coming up on high-bandwidth HDMI displays under a
number of configurations.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
index 9b16a08eb4d9f49c1d00b27fca9608e701dc2d5c..bf6d41fb0c9fe54ca08a23fb7ae6a0d088bf6714 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
@@ -27,10 +27,10 @@ void
 gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc)
 {
        struct nvkm_device *device = ior->disp->engine.subdev.device;
-       const u32 hoff = head * 0x800;
+       const u32 soff = nv50_ior_base(ior);
        const u32 ctrl = scdc & 0x3;
 
-       nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);
+       nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl);
 
        ior->tmds.high_speed = !!(scdc & 0x2);
 }