struct bcma_device *cc;
uint origidx = 0;
u32 w;
- uint intr_val = 0;
struct si_info *sii;
sii = (struct si_info *)sih;
cc = sii->icbus->drv_cc.core;
- INTR_OFF(sii, intr_val);
-
/* save current core index */
origidx = ai_coreidx(&sii->pub);
/* restore core index */
ai_setcoreidx(&sii->pub, origidx);
- INTR_RESTORE(sii, intr_val);
-
return w;
}
struct bcma_device *cc;
uint slowminfreq;
u16 fpdelay;
- uint intr_val = 0;
sii = (struct si_info *)sih;
if (ai_get_cccaps(sih) & CC_CAP_PMU) {
- INTR_OFF(sii, intr_val);
fpdelay = si_pmu_fast_pwrup_delay(sih);
- INTR_RESTORE(sii, intr_val);
return fpdelay;
}
return 0;
fpdelay = 0;
- INTR_OFF(sii, intr_val);
cc = ai_findcore(sih, CC_CORE_ID, 0);
- if (cc == NULL)
- goto done;
-
-
- slowminfreq = ai_slowclk_freq(sih, false, cc);
- fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2) * 1000000)
- + (slowminfreq - 1)) / slowminfreq;
-
- done:
- INTR_RESTORE(sii, intr_val);
+ if (cc) {
+ slowminfreq = ai_slowclk_freq(sih, false, cc);
+ fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2)
+ * 1000000) + (slowminfreq - 1)) / slowminfreq;
+ }
return fpdelay;
}
{
struct bcma_device *cc;
u32 scc;
- uint intr_val = 0;
/* chipcommon cores prior to rev6 don't support dynamic clock control */
if (ai_get_ccrev(&sii->pub) < 6)
return false;
- INTR_OFF(sii, intr_val);
cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
(ai_get_ccrev(&sii->pub) < 20))
- goto done;
+ return mode == CLK_FAST;
switch (mode) {
case CLK_FAST: /* FORCEHT, fast (pll) clock */
break;
}
- done:
- INTR_RESTORE(sii, intr_val);
return mode == CLK_FAST;
}