agp/intel: Add actual definitions of the Sandybridge PTE caching bits.

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 2547465d46584e15c8993086e2546f78872055de..c05e3e518268ac3cab497970f55371cc2c06acba 100644 (file)
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -60,6 +60,12 @@
 #define I810_PTE_LOCAL         0x00000002
 #define I810_PTE_VALID         0x00000001
 #define I830_PTE_SYSTEM_CACHED  0x00000006
+/* GT PTE cache control fields */
+#define GEN6_PTE_UNCACHED      0x00000002
+#define GEN6_PTE_LLC           0x00000004
+#define GEN6_PTE_LLC_MLC       0x00000006
+#define GEN6_PTE_GFDT          0x00000008
+
 #define I810_SMRAM_MISCC       0x70
 #define I810_GFX_MEM_WIN_SIZE  0x00010000
 #define I810_GFX_MEM_WIN_32M   0x00010000

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 2b1a0e96c71f84b51401733fbce68e8a8baecedc..ccd4b1e694d17b450aa4ee67fc2f51dc737939fe 100644 (file)
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -176,7 +176,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem,
        if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
            agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
        {
-               cache_bits = I830_PTE_SYSTEM_CACHED;
+               cache_bits = GEN6_PTE_LLC_MLC;
        }
 
        for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {