}
}
+static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn,
+ TCGReg ret, TCGReg src1, int src2, bool c_src2)
+{
+ tcg_out_opc_imm(s, insn, ret, src1, 0);
+
+ if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) {
+ /*
+ * The requested zero result does not match the insn, so adjust.
+ * Note that constraints put 'ret' in a new register, so the
+ * computation above did not clobber either 'src1' or 'src2'.
+ */
+ tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true,
+ src2, c_src2, ret, false);
+ }
+}
+
static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
{
TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0);
break;
+ case INDEX_op_clz_i32:
+ tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2);
+ break;
+ case INDEX_op_clz_i64:
+ tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2);
+ break;
+ case INDEX_op_ctz_i32:
+ tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2);
+ break;
+ case INDEX_op_ctz_i64:
+ tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2);
+ break;
+
case INDEX_op_add2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], false, true);
case INDEX_op_rotr_i64:
return C_O1_I2(r, r, ri);
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_ctz_i64:
+ return C_N1_I2(r, r, rM);
+
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
return C_O0_I2(rZ, rZ);
#define TCG_TARGET_HAS_eqv_i32 have_zbb
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
-#define TCG_TARGET_HAS_clz_i32 0
-#define TCG_TARGET_HAS_ctz_i32 0
+#define TCG_TARGET_HAS_clz_i32 have_zbb
+#define TCG_TARGET_HAS_ctz_i32 have_zbb
#define TCG_TARGET_HAS_ctpop_i32 have_zbb
#define TCG_TARGET_HAS_brcond2 1
#define TCG_TARGET_HAS_setcond2 1
#define TCG_TARGET_HAS_eqv_i64 have_zbb
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
-#define TCG_TARGET_HAS_clz_i64 0
-#define TCG_TARGET_HAS_ctz_i64 0
+#define TCG_TARGET_HAS_clz_i64 have_zbb
+#define TCG_TARGET_HAS_ctz_i64 have_zbb
#define TCG_TARGET_HAS_ctpop_i64 have_zbb
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1