]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/commitdiff
ARM: dts: meson: add the hardware random number generator
authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Thu, 15 Jun 2017 21:33:49 +0000 (23:33 +0200)
committerKevin Hilman <khilman@baylibre.com>
Fri, 16 Jun 2017 19:07:11 +0000 (12:07 -0700)
All supported Meson SoCs have a random number generator in CBUS.
Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number
register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two
32-bit random number registers. The existing meson-rng driver only
supports the lower 32-bit - but it still works fine on the older SoCs
apart from this small limitation.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm/boot/dts/meson.dtsi
arch/arm/boot/dts/meson8.dtsi
arch/arm/boot/dts/meson8b.dtsi

index 46706d74a14577995b9885610e35e36eb291a5f1..bf37606ba82ee7a73477f00d29cb6d133effcb72 100644 (file)
                        #size-cells = <1>;
                        ranges = <0x0 0xc1100000 0x200000>;
 
+                       hwrng: rng@8100 {
+                               compatible = "amlogic,meson-rng";
+                               reg = <0x8100 0x8>;
+                       };
+
                        uart_A: serial@84c0 {
                                compatible = "amlogic,meson-uart";
                                reg = <0x84c0 0x18>;
index df79a34a3530a8d9334eef70b2976c33827cf645..b4c5fdd7b45194dfd00b182975b95a6e4acd1b4b 100644 (file)
        clock-names = "stmmaceth";
 };
 
+&hwrng {
+       compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
+       clocks = <&clkc CLKID_RNG0>;
+       clock-names = "core";
+};
+
 &i2c_AO {
        clocks = <&clkc CLKID_CLK81>;
 };
index 1c09090ff4a51bb63fee06c07bdfe2158a36e223..a9d7074e6369db96a05d46b7a17eea20795bca5c 100644 (file)
        };
 };
 
+&hwrng {
+       compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
+       clocks = <&clkc CLKID_RNG0>;
+       clock-names = "core";
+};
+
 &L2 {
        arm,data-latency = <3 3 3>;
        arm,tag-latency = <2 2 2>;