drm/etnaviv: add PE perf domain

We need to iterate over all pixel pipelines to get overall value.

Changes from v4 -> v5:
- switch back to pixel pipe 0 to prevent GPU hang
- PIXELS_RENDERED_2D is exposed for 2D pipe

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
index f0cdf371663a8fb23d4b2e6ef2048a773d3414c7..9f933feabff23b24abede2859313aa1e77d88e51 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
@@ -62,6 +62,30 @@ static u32 perf_reg_read(struct etnaviv_gpu *gpu,
        return gpu_read(gpu, domain->profile_read);
 }
 
+static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
+       const struct etnaviv_pm_domain *domain,
+       const struct etnaviv_pm_signal *signal)
+{
+       u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
+       u32 value = 0;
+       unsigned i;
+
+       for (i = 0; i < gpu->identity.pixel_pipes; i++) {
+               clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
+               clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i);
+               gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
+               gpu_write(gpu, domain->profile_config, signal->data);
+               value += gpu_read(gpu, domain->profile_read);
+       }
+
+       /* switch back to pixel pipe 0 to prevent GPU hang */
+       clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
+       clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0);
+       gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
+
+       return value;
+}
+
 static const struct etnaviv_pm_domain doms_3d[] = {
        {
                .name = "HI",
@@ -95,10 +119,51 @@ static const struct etnaviv_pm_domain doms_3d[] = {
                                &perf_reg_read
                        }
                }
+       },
+       {
+               .name = "PE",
+               .profile_read = VIVS_MC_PROFILE_PE_READ,
+               .profile_config = VIVS_MC_PROFILE_CONFIG0,
+               .nr_signals = 5,
+               .signal = (const struct etnaviv_pm_signal[]) {
+                       {
+                               "PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
+                               VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE,
+                               &pipe_reg_read
+                       },
+                       {
+                               "PIXEL_COUNT_KILLED_BY_DEPTH_PIPE",
+                               VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE,
+                               &pipe_reg_read
+                       },
+                       {
+                               "PIXEL_COUNT_DRAWN_BY_COLOR_PIPE",
+                               VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE,
+                               &pipe_reg_read
+                       },
+                       {
+                               "PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE",
+                               VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE,
+                               &pipe_reg_read
+                       }
+               }
        }
 };
 
 static const struct etnaviv_pm_domain doms_2d[] = {
+       {
+               .name = "PE",
+               .profile_read = VIVS_MC_PROFILE_PE_READ,
+               .profile_config = VIVS_MC_PROFILE_CONFIG0,
+               .nr_signals = 1,
+               .signal = (const struct etnaviv_pm_signal[]) {
+                       {
+                               "PIXELS_RENDERED_2D",
+                               VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D,
+                               &pipe_reg_read
+                       }
+               }
+       }
 };
 
 static const struct etnaviv_pm_domain doms_vg[] = {