perf/x86: Enable free running PEBS for REGS_USER/INTR

Currently free running PEBS is disabled when user or interrupt
registers are requested. Most of the registers are actually
available in the PEBS record and can be supported.

So we just need to check for the supported registers and then
allow it: it is all except for the segment register.

For user registers this only works when the counter is limited
to ring 3 only, so this also needs to be checked.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20170831214630.21892-1-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 829e89cfcee2deff8b937806b16dd573d736a895..cfd91a03304de94e1e5c05e2d5d9193259b764a8 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2958,6 +2958,10 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
 
        if (event->attr.use_clockid)
                flags &= ~PERF_SAMPLE_TIME;
+       if (!event->attr.exclude_kernel)
+               flags &= ~PERF_SAMPLE_REGS_USER;
+       if (event->attr.sample_regs_user & ~PEBS_REGS)
+               flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
        return flags;
 }
 

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 4196f81ec0e1b0de71483cbc999837ec48b51f33..f7aaadf9331fb75587e74a42b041d78b2a014fc0 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -85,13 +85,15 @@ struct amd_nb {
  * Flags PEBS can handle without an PMI.
  *
  * TID can only be handled by flushing at context switch.
+ * REGS_USER can be handled for events limited to ring 3.
  *
  */
 #define PEBS_FREERUNNING_FLAGS \
        (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
        PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
        PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
-       PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR)
+       PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
+       PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)
 
 /*
  * A debug store configuration.
@@ -110,6 +112,26 @@ struct debug_store {
        u64     pebs_event_reset[MAX_PEBS_EVENTS];
 };
 
+#define PEBS_REGS \
+       (PERF_REG_X86_AX | \
+        PERF_REG_X86_BX | \
+        PERF_REG_X86_CX | \
+        PERF_REG_X86_DX | \
+        PERF_REG_X86_DI | \
+        PERF_REG_X86_SI | \
+        PERF_REG_X86_SP | \
+        PERF_REG_X86_BP | \
+        PERF_REG_X86_IP | \
+        PERF_REG_X86_FLAGS | \
+        PERF_REG_X86_R8 | \
+        PERF_REG_X86_R9 | \
+        PERF_REG_X86_R10 | \
+        PERF_REG_X86_R11 | \
+        PERF_REG_X86_R12 | \
+        PERF_REG_X86_R13 | \
+        PERF_REG_X86_R14 | \
+        PERF_REG_X86_R15)
+
 /*
  * Per register state.
  */