clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs

It may happen that clock framework finds optimal video PLL rate above
that which is really supported by HW.

User manual doesn't really say what is upper limit for video PLLs on
A83T. Because of that, use the maximum rate defined in BSP clk driver
which is 3 GHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 7d08015b980d33e7f53b5a5d48ee18894896fe6c..2d6555d7317058c1b892bc91dbd75dfe0fe1df6e 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -108,6 +108,7 @@ static struct ccu_nkmp pll_video0_clk = {
        .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
        .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
        .p              = _SUNXI_CCU_DIV(0, 2), /* output divider */
+       .max_rate       = 3000000000UL,
        .common         = {
                .reg            = 0x010,
                .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
@@ -220,6 +221,7 @@ static struct ccu_nkmp pll_video1_clk = {
        .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
        .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
        .p              = _SUNXI_CCU_DIV(0, 2), /* external divider p */
+       .max_rate       = 3000000000UL,
        .common         = {
                .reg            = 0x04c,
                .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,