target-arm: A64: List unsupported shift-imm opcodes

Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e6addf45f1bb1d922a3ba7baaf81efc8df9411b6..2b1ca64b199b476073c03a8e474d49b59d7355d2 100644 (file)
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
         handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
                                immh, immb, opcode, rn, rd);
         break;
-    default:
+    case 0x8: /* SRI */
+    case 0xc: /* SQSHLU */
+    case 0xe: /* SQSHL, UQSHL */
+    case 0x1f: /* FCVTZS, FCVTZU */
         unsupported_encoding(s, insn);
         break;
+    default:
+        unallocated_encoding(s);
+        break;
     }
 }
 
@@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
         handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
                                      opcode, rn, rd);
         break;
+    case 0x8: /* SRI */
+    case 0xc: /* SQSHLU */
+    case 0xe: /* SQSHL, UQSHL */
     case 0x1f: /* FCVTZS/ FCVTZU */
         unsupported_encoding(s, insn);
         return;
     default:
-        unsupported_encoding(s, insn);
+        unallocated_encoding(s);
         return;
     }
 }