return o;
}
-i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq, qemu_irq smi_irq,
- int kvm_enabled, FWCfgState *fw_cfg)
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq, qemu_irq smi_irq,
+ int kvm_enabled, FWCfgState *fw_cfg)
{
DeviceState *dev;
PIIX4PMState *s;
busdev = SYS_BUS_DEVICE(dev);
sysbus_connect_irq(busdev, 0, i2c_irq);
sysbus_mmio_map(busdev, 0, addr);
- s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
+ s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c");
}
DeviceState *key_dev;
DeviceState *wm8750_dev;
SysBusDevice *s;
- i2c_bus *i2c;
+ I2CBus *i2c;
int i;
unsigned long flash_size;
DriveInfo *dinfo;
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
pic[MP_GPIO_IRQ]);
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
- i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
+ i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL);
key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL);
{
DeviceState *dev;
qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
- i2c_bus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
+ I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
/* Attach a menelaus PM chip */
dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
MemoryRegion iomem;
PXA2xxI2CSlaveState *slave;
- i2c_bus *bus;
+ I2CBus *bus;
qemu_irq irq;
uint32_t offset;
uint32_t region_size;
DeviceState *dev;
SysBusDevice *i2c_dev;
PXA2xxI2CState *s;
- i2c_bus *i2cbus;
+ I2CBus *i2cbus;
dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
qdev_prop_set_uint32(dev, "size", region_size + 1);
return 0;
}
-i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
+I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
{
return s->bus;
}
qemu_irq mmc_irq[2];
PCIBus *pci_bus = NULL;
NICInfo *nd;
- i2c_bus *i2c;
+ I2CBus *i2c;
int n;
int done_nic = 0;
qemu_irq cpu_irq[4];
}
dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
- i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
+ i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_create_slave(i2c, "ds1338", 0x68);
/* Memory map for RealView Emulation Baseboard: */
static void spitz_i2c_setup(PXA2xxState *cpu)
{
/* Attach the CPU on one end of our I2C bus. */
- i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
+ I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
DeviceState *wm;
typedef struct {
SysBusDevice parent_obj;
- i2c_bus *bus;
+ I2CBus *bus;
qemu_irq irq;
MemoryRegion iomem;
uint32_t msa;
{
DeviceState *dev = DEVICE(sbd);
stellaris_i2c_state *s = STELLARIS_I2C(dev);
- i2c_bus *bus;
+ I2CBus *bus;
sysbus_init_irq(sbd, &s->irq);
bus = i2c_init_bus(dev, "i2c");
qemu_irq adc;
int sram_size;
int flash_size;
- i2c_bus *i2c;
+ I2CBus *i2c;
DeviceState *dev;
int i;
int j;
if (board->dc2 & (1 << 12)) {
dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, pic[8]);
- i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
+ i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
if (board->peripherals & BP_OLED_I2C) {
i2c_create_slave(i2c, "ssd0303", 0x3d);
}
static void tosa_tg_init(PXA2xxState *cpu)
{
- i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
+ I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
i2c_create_slave(bus, "tosa_dac", DAC_BASE);
ssi_create_slave(cpu->ssp[1], "tosa-ssp");
}
DeviceState *pl041;
PCIBus *pci_bus;
NICInfo *nd;
- i2c_bus *i2c;
+ I2CBus *i2c;
int n;
int done_smc = 0;
DriveInfo *dinfo;
sysbus_create_simple("pl031", 0x101e8000, pic[10]);
dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
- i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
+ i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
i2c_create_slave(i2c, "ds1338", 0x68);
/* Add PL041 AACI Interface to the LM4549 codec */
DriveInfo *dinfo;
int be;
void *z2_lcd;
- i2c_bus *bus;
+ I2CBus *bus;
DeviceState *wm;
if (!cpu_model) {
} bitbang_i2c_state;
struct bitbang_i2c_interface {
- i2c_bus *bus;
+ I2CBus *bus;
bitbang_i2c_state state;
int last_data;
int last_clock;
abort();
}
-bitbang_i2c_interface *bitbang_i2c_init(i2c_bus *bus)
+bitbang_i2c_interface *bitbang_i2c_init(I2CBus *bus)
{
bitbang_i2c_interface *s;
{
DeviceState *dev = DEVICE(sbd);
GPIOI2CState *s = GPIO_I2C(dev);
- i2c_bus *bus;
+ I2CBus *bus;
memory_region_init(&s->dummy_iomem, OBJECT(s), "gpio_i2c", 0);
sysbus_init_mmio(sbd, &s->dummy_iomem);
#define BITBANG_I2C_SDA 0
#define BITBANG_I2C_SCL 1
-bitbang_i2c_interface *bitbang_i2c_init(i2c_bus *bus);
+bitbang_i2c_interface *bitbang_i2c_init(I2CBus *bus);
int bitbang_i2c_set(bitbang_i2c_interface *i2c, int line, int level);
#endif
#include "hw/i2c/i2c.h"
-struct i2c_bus
+struct I2CBus
{
BusState qbus;
I2CSlave *current_dev;
};
#define TYPE_I2C_BUS "i2c-bus"
-#define I2C_BUS(obj) OBJECT_CHECK(i2c_bus, (obj), TYPE_I2C_BUS)
+#define I2C_BUS(obj) OBJECT_CHECK(I2CBus, (obj), TYPE_I2C_BUS)
static const TypeInfo i2c_bus_info = {
.name = TYPE_I2C_BUS,
.parent = TYPE_BUS,
- .instance_size = sizeof(i2c_bus),
+ .instance_size = sizeof(I2CBus),
};
static void i2c_bus_pre_save(void *opaque)
{
- i2c_bus *bus = opaque;
+ I2CBus *bus = opaque;
bus->saved_address = bus->current_dev ? bus->current_dev->address : -1;
}
static int i2c_bus_post_load(void *opaque, int version_id)
{
- i2c_bus *bus = opaque;
+ I2CBus *bus = opaque;
/* The bus is loaded before attached devices, so load and save the
current device id. Devices will check themselves as loaded. */
.pre_save = i2c_bus_pre_save,
.post_load = i2c_bus_post_load,
.fields = (VMStateField []) {
- VMSTATE_UINT8(saved_address, i2c_bus),
+ VMSTATE_UINT8(saved_address, I2CBus),
VMSTATE_END_OF_LIST()
}
};
/* Create a new I2C bus. */
-i2c_bus *i2c_init_bus(DeviceState *parent, const char *name)
+I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
{
- i2c_bus *bus;
+ I2CBus *bus;
bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
}
/* Return nonzero if bus is busy. */
-int i2c_bus_busy(i2c_bus *bus)
+int i2c_bus_busy(I2CBus *bus)
{
return bus->current_dev != NULL;
}
/* Returns non-zero if the address is not valid. */
/* TODO: Make this handle multiple masters. */
-int i2c_start_transfer(i2c_bus *bus, uint8_t address, int recv)
+int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
{
BusChild *kid;
I2CSlave *slave = NULL;
return 0;
}
-void i2c_end_transfer(i2c_bus *bus)
+void i2c_end_transfer(I2CBus *bus)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
bus->current_dev = NULL;
}
-int i2c_send(i2c_bus *bus, uint8_t data)
+int i2c_send(I2CBus *bus, uint8_t data)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
return -1;
}
-int i2c_recv(i2c_bus *bus)
+int i2c_recv(I2CBus *bus)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
return -1;
}
-void i2c_nack(i2c_bus *bus)
+void i2c_nack(I2CBus *bus)
{
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
static int i2c_slave_post_load(void *opaque, int version_id)
{
I2CSlave *dev = opaque;
- i2c_bus *bus;
+ I2CBus *bus;
bus = I2C_BUS(qdev_get_parent_bus(DEVICE(dev)));
if (bus->saved_address == dev->address) {
bus->current_dev = dev;
return sc->init(s);
}
-DeviceState *i2c_create_slave(i2c_bus *bus, const char *name, uint8_t addr)
+DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr)
{
DeviceState *dev;
SysBusDevice parent_obj;
MemoryRegion iomem;
- i2c_bus *bus;
+ I2CBus *bus;
qemu_irq irq;
uint8_t i2ccon;
MemoryRegion iomem;
qemu_irq irq;
qemu_irq drq[2];
- i2c_bus *bus;
+ I2CBus *bus;
uint8_t revision;
void *iclk;
type_register_static(&omap_i2c_info);
}
-i2c_bus *omap_i2c_bus(DeviceState *omap_i2c)
+I2CBus *omap_i2c_bus(DeviceState *omap_i2c)
{
OMAPI2CState *s = OMAP_I2C(omap_i2c);
return s->bus;
uint8_t read = s->smb_addr & 0x01;
uint8_t cmd = s->smb_cmd;
uint8_t addr = s->smb_addr >> 1;
- i2c_bus *bus = s->smbus;
+ I2CBus *bus = s->smbus;
SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
/* Transaction isn't exec if STS_DEV_ERR bit set */
}
/* Master device commands. */
-void smbus_quick_command(i2c_bus *bus, uint8_t addr, int read)
+void smbus_quick_command(I2CBus *bus, uint8_t addr, int read)
{
i2c_start_transfer(bus, addr, read);
i2c_end_transfer(bus);
}
-uint8_t smbus_receive_byte(i2c_bus *bus, uint8_t addr)
+uint8_t smbus_receive_byte(I2CBus *bus, uint8_t addr)
{
uint8_t data;
return data;
}
-void smbus_send_byte(i2c_bus *bus, uint8_t addr, uint8_t data)
+void smbus_send_byte(I2CBus *bus, uint8_t addr, uint8_t data)
{
i2c_start_transfer(bus, addr, 0);
i2c_send(bus, data);
i2c_end_transfer(bus);
}
-uint8_t smbus_read_byte(i2c_bus *bus, uint8_t addr, uint8_t command)
+uint8_t smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command)
{
uint8_t data;
i2c_start_transfer(bus, addr, 0);
return data;
}
-void smbus_write_byte(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t data)
+void smbus_write_byte(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t data)
{
i2c_start_transfer(bus, addr, 0);
i2c_send(bus, command);
i2c_end_transfer(bus);
}
-uint16_t smbus_read_word(i2c_bus *bus, uint8_t addr, uint8_t command)
+uint16_t smbus_read_word(I2CBus *bus, uint8_t addr, uint8_t command)
{
uint16_t data;
i2c_start_transfer(bus, addr, 0);
return data;
}
-void smbus_write_word(i2c_bus *bus, uint8_t addr, uint8_t command, uint16_t data)
+void smbus_write_word(I2CBus *bus, uint8_t addr, uint8_t command, uint16_t data)
{
i2c_start_transfer(bus, addr, 0);
i2c_send(bus, command);
i2c_end_transfer(bus);
}
-int smbus_read_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data)
+int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data)
{
int len;
int i;
return len;
}
-void smbus_write_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data,
+void smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
int len)
{
int i;
type_init(smbus_eeprom_register_types)
-void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom,
+void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
const uint8_t *eeprom_spd, int eeprom_spd_size)
{
int i;
dc->cannot_instantiate_with_device_add_yet = true;
}
-i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
+I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
PCIDevice *d =
pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
{
DeviceState *dev = DEVICE(sbd);
VersatileI2CState *s = VERSATILE_I2C(dev);
- i2c_bus *bus;
+ I2CBus *bus;
bus = i2c_init_bus(dev, "i2c");
s->bitbang = bitbang_i2c_init(bus);
}
if (pci_enabled && acpi_enabled) {
- i2c_bus *smbus;
+ I2CBus *smbus;
smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
/* TODO: Populate SPD eeprom data. */
return 0;
}
-i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq)
+I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq)
{
PCIDevice *dev;
VT686PMState *s;
qemu_irq *cpu_exit_irq;
PCIBus *pci_bus;
ISABus *isa_bus;
- i2c_bus *smbus;
+ I2CBus *smbus;
int i;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
MIPSCPU *cpu;
qemu_irq *isa_irq;
qemu_irq *cpu_exit_irq;
int piix4_devfn;
- i2c_bus *smbus;
+ I2CBus *smbus;
int i;
DriveInfo *dinfo;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
MemoryRegion dram1_mem;
MemoryRegion boot_secondary;
MemoryRegion bootreg_mem;
- i2c_bus *i2c_if[EXYNOS4210_I2C_NUMBER];
+ I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
} Exynos4210State;
void exynos4210_write_secondary(ARMCPU *cpu,
void omap_mmc_enable(struct omap_mmc_s *s, int enable);
/* omap_i2c.c */
-i2c_bus *omap_i2c_bus(DeviceState *omap_i2c);
+I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
typedef struct PXA2xxI2CState PXA2xxI2CState;
PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t page_size);
-i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
+I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;
uint8_t address;
};
-i2c_bus *i2c_init_bus(DeviceState *parent, const char *name);
+I2CBus *i2c_init_bus(DeviceState *parent, const char *name);
void i2c_set_slave_address(I2CSlave *dev, uint8_t address);
-int i2c_bus_busy(i2c_bus *bus);
-int i2c_start_transfer(i2c_bus *bus, uint8_t address, int recv);
-void i2c_end_transfer(i2c_bus *bus);
-void i2c_nack(i2c_bus *bus);
-int i2c_send(i2c_bus *bus, uint8_t data);
-int i2c_recv(i2c_bus *bus);
+int i2c_bus_busy(I2CBus *bus);
+int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv);
+void i2c_end_transfer(I2CBus *bus);
+void i2c_nack(I2CBus *bus);
+int i2c_send(I2CBus *bus, uint8_t data);
+int i2c_recv(I2CBus *bus);
#define FROM_I2C_SLAVE(type, dev) DO_UPCAST(type, i2c, dev)
-DeviceState *i2c_create_slave(i2c_bus *bus, const char *name, uint8_t addr);
+DeviceState *i2c_create_slave(I2CBus *bus, const char *name, uint8_t addr);
/* wm8750.c */
void wm8750_data_req_set(DeviceState *dev,
#define PM_SMBUS_H
typedef struct PMSMBus {
- i2c_bus *smbus;
+ I2CBus *smbus;
MemoryRegion io;
uint8_t smb_stat;
};
/* Master device commands. */
-void smbus_quick_command(i2c_bus *bus, uint8_t addr, int read);
-uint8_t smbus_receive_byte(i2c_bus *bus, uint8_t addr);
-void smbus_send_byte(i2c_bus *bus, uint8_t addr, uint8_t data);
-uint8_t smbus_read_byte(i2c_bus *bus, uint8_t addr, uint8_t command);
-void smbus_write_byte(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t data);
-uint16_t smbus_read_word(i2c_bus *bus, uint8_t addr, uint8_t command);
-void smbus_write_word(i2c_bus *bus, uint8_t addr, uint8_t command, uint16_t data);
-int smbus_read_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data);
-void smbus_write_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data,
+void smbus_quick_command(I2CBus *bus, uint8_t addr, int read);
+uint8_t smbus_receive_byte(I2CBus *bus, uint8_t addr);
+void smbus_send_byte(I2CBus *bus, uint8_t addr, uint8_t data);
+uint8_t smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command);
+void smbus_write_byte(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t data);
+uint16_t smbus_read_word(I2CBus *bus, uint8_t addr, uint8_t command);
+void smbus_write_word(I2CBus *bus, uint8_t addr, uint8_t command, uint16_t data);
+int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data);
+void smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
int len);
-void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom,
+void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
const uint8_t *eeprom_spd, int size);
#endif
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc);
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
-i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
/* acpi_piix.c */
-i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq, qemu_irq smi_irq,
- int kvm_enabled, FWCfgState *fw_cfg);
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq, qemu_irq smi_irq,
+ int kvm_enabled, FWCfgState *fw_cfg);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
/* hpet.c */
ISABus *vt82c686b_init(PCIBus * bus, int devfn);
void vt82c686b_ac97_init(PCIBus *bus, int devfn);
void vt82c686b_mc97_init(PCIBus *bus, int devfn);
-i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq);
+I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq);
#endif
typedef struct CharDriverState CharDriverState;
typedef struct MACAddr MACAddr;
typedef struct NetClientState NetClientState;
-typedef struct i2c_bus i2c_bus;
+typedef struct I2CBus I2CBus;
typedef struct ISABus ISABus;
typedef struct ISADevice ISADevice;
typedef struct SMBusDevice SMBusDevice;