/* Always disable the PLL - it is not safe to leave it running
* while reprogramming it.
*/
- reg = snd_soc_read(codec, WM8580_PWRDN2);
- snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
+ snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, pwr_mask);
if (!freq_in || !freq_out)
return 0;
snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
/* All done, turn it on */
- reg = snd_soc_read(codec, WM8580_PWRDN2);
- snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
+ snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, 0);
return 0;
}
static int wm8580_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
- u16 reg;
switch (level) {
case SND_SOC_BIAS_ON:
case SND_SOC_BIAS_PREPARE:
case SND_SOC_BIAS_STANDBY:
if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
/* Power up and get individual control of the DACs */
- reg = snd_soc_read(codec, WM8580_PWRDN1);
- reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
- snd_soc_write(codec, WM8580_PWRDN1, reg);
+ snd_soc_update_bits(codec, WM8580_PWRDN1,
+ WM8580_PWRDN1_PWDN |
+ WM8580_PWRDN1_ALLDACPD, 0);
/* Make VMID high impedance */
- reg = snd_soc_read(codec, WM8580_ADC_CONTROL1);
- reg &= ~0x100;
- snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
+ snd_soc_update_bits(codec, WM8580_ADC_CONTROL1,
+ 0x100, 0);
}
break;
case SND_SOC_BIAS_OFF:
- reg = snd_soc_read(codec, WM8580_PWRDN1);
- snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
+ snd_soc_update_bits(codec, WM8580_PWRDN1,
+ WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
break;
}
codec->dapm.bias_level = level;