]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
net/mlx5: Let user configure event_eq_size param
authorShay Drory <shayd@nvidia.com>
Wed, 13 Oct 2021 06:57:54 +0000 (09:57 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Mon, 25 Oct 2021 20:51:20 +0000 (13:51 -0700)
Event EQ is an EQ which received the notification of almost all the
events generated by the NIC.
Currently, each event EQ is taking 512KB of memory. This size is not
needed in most use cases, and is critical with large scale. Hence,
allow user to configure the size of the event EQ.

For example to reduce event EQ size to 64, execute::
$ devlink resource set pci/0000:00:0b.0 path /event_eq_size/ size 64
$ devlink dev reload pci/0000:00:0b.0

Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Documentation/networking/devlink/mlx5.rst
drivers/net/ethernet/mellanox/mlx5/core/devlink.h
drivers/net/ethernet/mellanox/mlx5/core/devlink_res.c
drivers/net/ethernet/mellanox/mlx5/core/eq.c
include/linux/mlx5/eq.h

index 4e602057029215a1475430e9cb95488078983b02..5b77863f9c88f0c2b0da0a631e145ab8fa5cc3a8 100644 (file)
@@ -57,6 +57,10 @@ Resources
    * - ``comp_eq_size``
      - Control the size of I/O completion EQs.
        * The default value is 1024, and the range is between 64 and 4096.
+   * - ``event_eq_size``
+     - Control the size of the asynchronous control events EQ.
+       * The default value is 4096, and the range is between 64 and 4096.
+
 
 Info versions
 =============
index 4192f23b14465b078d890ab27d7f8f4812d81d75..674415fd0b3a7452aeebe1e8f38c947448b41c5d 100644 (file)
@@ -8,6 +8,7 @@
 
 enum mlx5_devlink_resource_id {
        MLX5_DL_RES_COMP_EQ = 1,
+       MLX5_DL_RES_ASYNC_EQ,
 
        __MLX5_ID_RES_MAX,
        MLX5_ID_RES_MAX = __MLX5_ID_RES_MAX - 1,
index 3beedfb8534a76f6fb6ef76e20c4b73c3df63c5b..549d23745942eb73f39567381e5770ac98a87f98 100644 (file)
@@ -7,6 +7,7 @@
 enum {
        MLX5_EQ_MIN_SIZE = 64,
        MLX5_EQ_MAX_SIZE = 4096,
+       MLX5_NUM_ASYNC_EQE = 4096,
        MLX5_COMP_EQ_SIZE = 1024,
 };
 
@@ -23,13 +24,35 @@ static int comp_eq_res_register(struct mlx5_core_dev *dev)
                                         &comp_eq_size);
 }
 
+static int async_eq_resource_register(struct mlx5_core_dev *dev)
+{
+       struct devlink_resource_size_params async_eq_size;
+       struct devlink *devlink = priv_to_devlink(dev);
+
+       devlink_resource_size_params_init(&async_eq_size, MLX5_EQ_MIN_SIZE,
+                                         MLX5_EQ_MAX_SIZE, 1, DEVLINK_RESOURCE_UNIT_ENTRY);
+       return devlink_resource_register(devlink, "event_eq_size",
+                                        MLX5_NUM_ASYNC_EQE, MLX5_DL_RES_ASYNC_EQ,
+                                        DEVLINK_RESOURCE_ID_PARENT_TOP,
+                                        &async_eq_size);
+}
+
 void mlx5_devlink_res_register(struct mlx5_core_dev *dev)
 {
        int err;
 
        err = comp_eq_res_register(dev);
        if (err)
-               mlx5_core_err(dev, "Failed to register resources, err = %d\n", err);
+               goto err_msg;
+
+       err = async_eq_resource_register(dev);
+       if (err)
+               goto err;
+       return;
+err:
+       devlink_resources_unregister(priv_to_devlink(dev), NULL);
+err_msg:
+       mlx5_core_err(dev, "Failed to register resources, err = %d\n", err);
 }
 
 void mlx5_devlink_res_unregister(struct mlx5_core_dev *dev)
@@ -39,6 +62,7 @@ void mlx5_devlink_res_unregister(struct mlx5_core_dev *dev)
 
 static const size_t default_vals[MLX5_ID_RES_MAX + 1] = {
        [MLX5_DL_RES_COMP_EQ] = MLX5_COMP_EQ_SIZE,
+       [MLX5_DL_RES_ASYNC_EQ] = MLX5_NUM_ASYNC_EQE,
 };
 
 size_t mlx5_devlink_res_size(struct mlx5_core_dev *dev, enum mlx5_devlink_resource_id id)
index 4dda6e2a4cbc3be2ab8ebcb5d851c6ea671d5d61..31e69067284b8105426bdc92ab823fb25580eeff 100644 (file)
@@ -647,7 +647,7 @@ static int create_async_eqs(struct mlx5_core_dev *dev)
 
        param = (struct mlx5_eq_param) {
                .irq_index = MLX5_IRQ_EQ_CTRL,
-               .nent = MLX5_NUM_ASYNC_EQE,
+               .nent = mlx5_devlink_res_size(dev, MLX5_DL_RES_ASYNC_EQ),
        };
 
        gather_async_events_mask(dev, param.mask);
index ea3ff5a8ced3e4804d62bb5c569051a93d0b1bf4..11161e4276088c918cda269ae1556943d8b7497c 100644 (file)
@@ -5,7 +5,6 @@
 #define MLX5_CORE_EQ_H
 
 #define MLX5_NUM_CMD_EQE   (32)
-#define MLX5_NUM_ASYNC_EQE (0x1000)
 #define MLX5_NUM_SPARE_EQE (0x80)
 
 struct mlx5_eq;