Revert "x86/idle: Disable IBRS entering idle and enable it on wakeup"

CVE-2017-5753 (revert embargoed)
CVE-2017-5715 (revert embargoed)

This reverts commit 5521b04afda1d683c1ebad6c25c2529a88e6f061.

Signed-off-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h
index f15120ada161641cc4d0cd02896eabe06b13e6a3..bda3c27f0da06c494bac1faf99abb273f9c06ae3 100644 (file)
--- a/arch/x86/include/asm/mwait.h
+++ b/arch/x86/include/asm/mwait.h
@@ -5,8 +5,6 @@
 #include <linux/sched/idle.h>
 
 #include <asm/cpufeature.h>
-#include <asm/spec_ctrl.h>
-#include <asm/microcode.h>
 
 #define MWAIT_SUBSTATE_MASK            0xf
 #define MWAIT_CSTATE_MASK              0xf
@@ -107,15 +105,9 @@ static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
                        mb();
                }
 
-               if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
-                       native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
-
                __monitor((void *)&current_thread_info()->flags, 0, 0);
                if (!need_resched())
                        __mwait(eax, ecx);
-
-               if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
-                       native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
        }
        current_clr_polling();
 }

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 3adb3806a28495fcd5a27fabf52cfae17a8cbaea..07e6218ad7d922ab84c709415ee712d0403b50d4 100644 (file)
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -447,19 +447,11 @@ static __cpuidle void mwait_idle(void)
                        mb(); /* quirk */
                }
 
-               if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
-                        native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
-
                __monitor((void *)&current_thread_info()->flags, 0, 0);
-               if (!need_resched()) {
+               if (!need_resched())
                        __sti_mwait(0, 0);
-                       if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
-                               native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
-               } else {
-                       if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
-                               native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
+               else
                        local_irq_enable();
-               }
                trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
        } else {
                local_irq_enable();

diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c
index b088463973e4b2fc4d6589dbf0913e4a2fac41fc..cf2ac227c2aca27c4d44e6d49768e94586c13471 100644 (file)
--- a/arch/x86/lib/delay.c
+++ b/arch/x86/lib/delay.c
@@ -26,8 +26,6 @@
 # include <asm/smp.h>
 #endif
 
-#define IBRS_DISABLE_THRESHOLD 1000
-
 /* simple loop based delay: */
 static void delay_loop(unsigned long loops)
 {
@@ -107,10 +105,6 @@ static void delay_mwaitx(unsigned long __loops)
        for (;;) {
                delay = min_t(u64, MWAITX_MAX_LOOPS, loops);
 
-               if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
-                       (delay > IBRS_DISABLE_THRESHOLD))
-                       native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
-
                /*
                 * Use cpu_tss_rw as a cacheline-aligned, seldomly
                 * accessed per-cpu variable as the monitor target.
@@ -124,10 +118,6 @@ static void delay_mwaitx(unsigned long __loops)
                 */
                __mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
 
-               if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
-                       (delay > IBRS_DISABLE_THRESHOLD))
-                       native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
-
                end = rdtsc_ordered();
 
                if (loops <= end - start)