pinctrl: qcom: ipq4019: fix register offsets

For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb9f16ab3add453d1d066a2d920bbb76d1f93992..b68ae424cee247d51541d4ceb36aaa8c8c9132f6 100644 (file)
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
                        qca_mux_##f14                   \
                },                                      \
                .nfuncs = 15,                           \
-               .ctl_reg = 0x1000 + 0x10 * id,          \
-               .io_reg = 0x1004 + 0x10 * id,           \
-               .intr_cfg_reg = 0x1008 + 0x10 * id,     \
-               .intr_status_reg = 0x100c + 0x10 * id,  \
-               .intr_target_reg = 0x400 + 0x4 * id,    \
+               .ctl_reg = 0x0 + 0x1000 * id,           \
+               .io_reg = 0x4 + 0x1000 * id,            \
+               .intr_cfg_reg = 0x8 + 0x1000 * id,      \
+               .intr_status_reg = 0xc + 0x1000 * id,   \
+               .intr_target_reg = 0x8 + 0x1000 * id,   \
                .mux_bit = 2,                   \
                .pull_bit = 0,                  \
                .drv_bit = 6,                   \