Automated merge of kernel.org:/home/rmk/linux-2.6-rmk.git

diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 16cad2c2497cfc6ca033a36f2867e09e809ee5d4..5786ccad938cef12878a7c5a19db33617e16c50d 100644 (file)
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -18,6 +18,11 @@
 
 #include <asm/arch/pxa-regs.h>
 
+#ifdef CONFIG_PXA27x                   // workaround for Errata 50
+#define MDREFR_KDIV    0x200a4000      // all banks
+#define CCCR_SLEEP     0x00000107      // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
+#endif
+
                .text
 
 /*
@@ -28,7 +33,9 @@
 
 ENTRY(pxa_cpu_suspend)
 
+#ifndef CONFIG_IWMMXT
        mra     r2, r3, acc0
+#endif
        stmfd   sp!, {r2 - r12, lr}             @ save registers on stack
 
        @ get coprocessor registers
@@ -61,14 +68,23 @@ ENTRY(pxa_cpu_suspend)
        @ prepare value for sleep mode
        mov     r1, #3                          @ sleep mode
 
-       @ prepare to put SDRAM into self-refresh manually
+       @ prepare pointer to physical address 0 (virtual mapping in generic.c)
+       mov     r2, #UNCACHED_PHYS_0
+
+       @ prepare SDRAM refresh settings
        ldr     r4, =MDREFR
        ldr     r5, [r4]
+
+       @ enable SDRAM self-refresh mode
        orr     r5, r5, #MDREFR_SLFRSH
 
-       @ prepare pointer to physical address 0 (virtual mapping in generic.c)
-       mov     r2, #UNCACHED_PHYS_0
+#ifdef CONFIG_PXA27x
+       @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
+       ldr     r6, =MDREFR_KDIV
+       orr     r5, r5, r6
+#endif
 
+#ifdef CONFIG_PXA25x
        @ Intel PXA255 Specification Update notes problems
        @ about suspending with PXBus operating above 133MHz
        @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
@@ -100,6 +116,18 @@ ENTRY(pxa_cpu_suspend)
        mov     r0, #0
        mcr     p14, 0, r0, c6, c0, 0
        orr     r0, r0, #2                      @ initiate change bit
+#endif
+#ifdef CONFIG_PXA27x
+       @ Intel PXA270 Specification Update notes problems sleeping
+       @ with core operating above 91 MHz
+       @ (see Errata 50, ...processor does not exit from sleep...)
+
+       ldr     r6, =CCCR
+       ldr     r8, [r6]                @ keep original value for resume
+
+       ldr     r7, =CCCR_SLEEP         @ prepare CCCR sleep value
+       mov     r0, #0x2                @ prepare value for CLKCFG
+#endif
 
        @ align execution to a cache line
        b       1f
@@ -111,6 +139,7 @@ ENTRY(pxa_cpu_suspend)
        @ All needed values are now in registers.
        @ These last instructions should be in cache
 
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
        @ initiate the frequency change...
        str     r7, [r6]
        mcr     p14, 0, r0, c6, c0, 0
@@ -118,14 +147,27 @@ ENTRY(pxa_cpu_suspend)
        @ restore the original cpu speed value for resume
        str     r8, [r6]
 
-       @ put SDRAM into self-refresh
-       str     r5, [r4]
+       @ need 6 13-MHz cycles before changing PWRMODE
+       @ just set frequency to 91-MHz... 6*91/13 = 42
+
+       mov     r0, #42
+10:    subs    r0, r0, #1
+       bne     10b
+#endif
+
+       @ Do not reorder...
+       @ Intel PXA270 Specification Update notes problems performing
+       @ external accesses after SDRAM is put in self-refresh mode
+       @ (see Errata 39 ...hangs when entering self-refresh mode)
 
        @ force address lines low by reading at physical address 0
        ldr     r3, [r2]
 
+       @ put SDRAM into self-refresh
+       str     r5, [r4]
+
        @ enter sleep mode
-       mcr     p14, 0, r1, c7, c0, 0
+       mcr     p14, 0, r1, c7, c0, 0           @ PWRMODE
 
 20:    b       20b                             @ loop waiting for sleep
 
@@ -188,7 +230,9 @@ resume_after_mmu:
        bl      cpu_xscale_proc_init
 #endif
        ldmfd   sp!, {r2, r3}
+#ifndef CONFIG_IWMMXT
        mar     acc0, r2, r3
+#endif
        ldmfd   sp!, {r4 - r12, pc}             @ return to caller
 
 

diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index 7ae8e1f45bc1753d02292e10170cf930113d68a3..385b07d510daed2630bdd2748924a428d73619cd 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -14,6 +14,7 @@
  *    26-06-2003     BJD     Finished off definitions for register addresses
  *    12-03-2004     BJD     Updated include protection
  *    07-03-2005     BJD     Added FIFO size flags and S3C2440 MPLL
+ *    05-04-2005     LCVR    Added IISFCON definitions for the S3C2400
  */
 
 #ifndef __ASM_ARCH_REGS_IIS_H
@@ -68,5 +69,14 @@
 #define S3C2410_IISFCON_RXMASK   (0x3f)
 #define S3C2410_IISFCON_RXSHIFT          (0)
 
+#define S3C2400_IISFCON_TXDMA     (1<<11)
+#define S3C2400_IISFCON_RXDMA     (1<<10)
+#define S3C2400_IISFCON_TXENABLE  (1<<9)
+#define S3C2400_IISFCON_RXENABLE  (1<<8)
+#define S3C2400_IISFCON_TXMASK   (0x07 << 4)
+#define S3C2400_IISFCON_TXSHIFT          (4)
+#define S3C2400_IISFCON_RXMASK   (0x07)
+#define S3C2400_IISFCON_RXSHIFT          (0)
+
 #define S3C2410_IISFIFO  (0x10)
 #endif /* __ASM_ARCH_REGS_IIS_H */

diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index 1a1328ac0d79bdc9c0fea701657d78d70f163394..a2d7d0cec04234b08b9fa5187dd0c70f5b9e33f1 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -12,6 +12,7 @@
  *  Changelog:
  *     29-Sep-2004  BJD  Initial include for Linux
  *      10-Mar-2005  LCVR Changed S3C2410_VA to S3C24XX_VA
+ *      04-Apr-2005  LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions
  *
 */
 
@@ -183,6 +184,12 @@
 #define S3C2410_REFRESH_TRP_3clk       (1<<20)
 #define S3C2410_REFRESH_TRP_4clk       (2<<20)
 
+#define S3C2400_REFRESH_DRAM_TRP_MASK   (3<<20)
+#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
+#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
+#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
+#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
+
 #define S3C2410_REFRESH_TSRC_MASK      (3<<18)
 #define S3C2410_REFRESH_TSRC_4clk      (0<<18)
 #define S3C2410_REFRESH_TSRC_5clk      (1<<18)
@@ -205,6 +212,7 @@
 #define S3C2410_BANKSIZE_4M            (0x5 << 0)
 #define S3C2410_BANKSIZE_2M            (0x4 << 0)
 #define S3C2410_BANKSIZE_MASK          (0x7 << 0)
+#define S3C2400_BANKSIZE_MASK           (0x4 << 0)
 #define S3C2410_BANKSIZE_SCLK_EN       (1<<4)
 #define S3C2410_BANKSIZE_SCKE_EN       (1<<5)
 #define S3C2410_BANKSIZE_BURST         (1<<7)

diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h
index cb502a88158b2ad4a892c641aac5657ee25cc309..338217858c730a55b4f5edf4f8214ede33a25639 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ b/include/asm-arm/arch-s3c2410/regs-spi.h
@@ -12,6 +12,7 @@
  *    20-04-2004     KF      Created file
  *    04-10-2004     BJD     Removed VA address (no longer mapped)
  *                          tidied file for submission
+ *    03-04-2005     LCVR    Added S3C2400_SPPIN_nCS definition
  */
 
 #ifndef __ASM_ARCH_REGS_SPI_H
@@ -46,6 +47,7 @@
 
 #define S3C2410_SPPIN_ENMUL      (1<<2)        /* Multi Master Error detect */
 #define S3C2410_SPPIN_RESERVED   (1<<1)
+#define S3C2400_SPPIN_nCS        (1<<1)        /* SPI Card Select */
 #define S3C2410_SPPIN_KEEP       (1<<0)        /* Master Out keep */
 
 

diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index ad4252e27799b02a8d9175c86b568d9da70e1ddf..d7a4a8354fa9854be8a2bc23203a0336b57b93fa 100644 (file)
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -16,6 +16,7 @@
  *  12-Oct-2004 BJD  Take account of debug uart configuration
  *  15-Nov-2004 BJD  Fixed uart configuration
  *  22-Feb-2005 BJD  Added watchdog to uncompress
+ *  04-Apr-2005 LCVR Added support to S3C2400 (no cpuid at GSTATUS1)
 */
 
 #ifndef __ASM_ARCH_UNCOMPRESS_H
@@ -69,9 +70,12 @@ uart_rd(unsigned int reg)
 static void
 putc(char ch)
 {
-       int cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
+       int cpuid = S3C2410_GSTATUS1_2410;
 
+#ifndef CONFIG_CPU_S3C2400
+       cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
        cpuid &= S3C2410_GSTATUS1_IDMASK;
+#endif
 
        if (ch == '\n')
                putc('\r');    /* expand newline to \r\n */

diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h
index 2a8ab162412fe70a9b78ab65cee951edd918e3fe..e50c4a39b699779f9af151397eeeb022ff2da0f5 100644 (file)
--- a/include/asm-arm/string.h
+++ b/include/asm-arm/string.h
@@ -29,15 +29,22 @@ extern void __memzero(void *ptr, __kernel_size_t n);
 
 #define memset(p,v,n)                                                  \
        ({                                                              \
-               if ((n) != 0) {                                         \
+               void *__p = (p); size_t __n = n;                        \
+               if ((__n) != 0) {                                       \
                        if (__builtin_constant_p((v)) && (v) == 0)      \
-                               __memzero((p),(n));                     \
+                               __memzero((__p),(__n));                 \
                        else                                            \
-                               memset((p),(v),(n));                    \
+                               memset((__p),(v),(__n));                \
                }                                                       \
-               (p);                                                    \
+               (__p);                                                  \
        })
 
-#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
+#define memzero(p,n)                                                   \
+       ({                                                              \
+               void *__p = (p); size_t __n = n;                        \
+               if ((__n) != 0)                                         \
+                       __memzero((__p),(__n));                         \
+               (__p);                                                  \
+        })
 
 #endif