arm64: dts: hip05: Append all gicv3 ITS entries

There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index ed31f1967687a39f476175c998ec6a8c46663fd1..c1b1a32939ed5e131df5e7f7963b90c2053d5659 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -246,11 +246,29 @@
                      <0x0 0xfe020000 0 0x10000>;       /* GICV */
                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-               its_totems: interrupt-controller@8c000000 {
+               its_peri: interrupt-controller@8c000000 {
                        compatible = "arm,gic-v3-its";
                        msi-controller;
                        reg = <0x0 0x8c000000 0x0 0x40000>;
                };
+
+               its_m3: interrupt-controller@a3000000 {
+                       compatible = "arm,gic-v3-its";
+                       msi-controller;
+                       reg = <0x0 0xa3000000 0x0 0x40000>;
+               };
+
+               its_pcie: interrupt-controller@b7000000 {
+                       compatible = "arm,gic-v3-its";
+                       msi-controller;
+                       reg = <0x0 0xb7000000 0x0 0x40000>;
+               };
+
+               its_dsa: interrupt-controller@c6000000 {
+                       compatible = "arm,gic-v3-its";
+                       msi-controller;
+                       reg = <0x0 0xc6000000 0x0 0x40000>;
+               };
        };
 
        timer {