]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commitdiff
ASoC: SOF: Intel: hda: Add helper function to program ICCMAX stream
authorRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Wed, 26 Aug 2020 18:45:27 +0000 (11:45 -0700)
committerMark Brown <broonie@kernel.org>
Thu, 27 Aug 2020 13:22:19 +0000 (14:22 +0100)
For some platforms, the recommended HW sequence for FW boot involves
starting a specially crafted capture stream before powering
on the DSP cores. Add a helper function to define the minimal
recommended stream programming sequence for this stream.

Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20200826184532.1612070-4-ranjani.sridharan@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/hda-stream.c
sound/soc/sof/intel/hda.h

index 1bda14c3590cd154f24532b4bc082af6408149a9..0e09ede922c7a074bbf78c7f072a07e948e17d77 100644 (file)
@@ -23,6 +23,8 @@
 #include "../sof-audio.h"
 #include "hda.h"
 
+#define HDA_LTRP_GB_VALUE_US   95
+
 /*
  * set up one of BDL entries for a stream
  */
@@ -322,6 +324,73 @@ int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
        return 0;
 }
 
+/* minimal recommended programming for ICCMAX stream */
+int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
+                                   struct snd_dma_buffer *dmab,
+                                   struct snd_pcm_hw_params *params)
+{
+       struct hdac_bus *bus = sof_to_bus(sdev);
+       struct hdac_stream *hstream = &stream->hstream;
+       int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
+       int ret;
+       u32 mask = 0x1 << hstream->index;
+
+       if (!stream) {
+               dev_err(sdev->dev, "error: no stream available\n");
+               return -ENODEV;
+       }
+
+       if (hstream->posbuf)
+               *hstream->posbuf = 0;
+
+       /* reset BDL address */
+       snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+                         0x0);
+       snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+                         0x0);
+
+       hstream->frags = 0;
+
+       ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
+       if (ret < 0) {
+               dev_err(sdev->dev, "error: set up of BDL failed\n");
+               return ret;
+       }
+
+       /* program BDL address */
+       snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
+                         (u32)hstream->bdl.addr);
+       snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
+                         upper_32_bits(hstream->bdl.addr));
+
+       /* program cyclic buffer length */
+       snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
+                         sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
+                         hstream->bufsize);
+
+       /* program last valid index */
+       snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+                               sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
+                               0xffff, (hstream->frags - 1));
+
+       /* decouple host and link DMA, enable DSP features */
+       snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
+                               mask, mask);
+
+       /* Follow HW recommendation to set the guardband value to 95us during FW boot */
+       snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
+
+       /* start DMA */
+       snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
+                               SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START);
+
+       return 0;
+}
+
 /*
  * prepare for common hdac registers settings, for both code loader
  * and normal stream.
index fe452f0d0ec73ce38ad84587c8d3f0a3ea02bce3..100eaaeecb4dd0fc77fda76e10a70cbf7ed6cd04 100644 (file)
 /* Intel Vendor Specific Registers */
 #define HDA_VS_INTEL_EM2               0x1030
 #define HDA_VS_INTEL_EM2_L1SEN         BIT(13)
+#define HDA_VS_INTEL_LTRP_GB_MASK      0x3F
 
 /*  HIPCI */
 #define HDA_DSP_REG_HIPCI_BUSY         BIT(31)
@@ -546,6 +547,9 @@ int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
                             struct hdac_ext_stream *stream,
                             struct snd_dma_buffer *dmab,
                             struct snd_pcm_hw_params *params);
+int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
+                                   struct snd_dma_buffer *dmab,
+                                   struct snd_pcm_hw_params *params);
 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
                           struct hdac_ext_stream *stream, int cmd);
 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);