drm/nouveau/falcon: better detection of debug register

Not all falcons have a debug register, and it is not always found at the
same offset.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c
index 19b9d44ae1a964f77fe12a8d4275806655e7fd8b..a4c6ee6ffde65c45ad164fec770c1d82cf837acb 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c
@@ -170,6 +170,7 @@ nvkm_falcon_ctor(const struct nvkm_falcon_func *func,
                 struct nvkm_subdev *subdev, const char *name, u32 addr,
                 struct nvkm_falcon *falcon)
 {
+       u32 debug_reg;
        u32 reg;
 
        falcon->func = func;
@@ -189,8 +190,30 @@ nvkm_falcon_ctor(const struct nvkm_falcon_func *func,
        falcon->code.limit = (reg & 0x1ff) << 8;
        falcon->data.limit = (reg & 0x3fe00) >> 1;
 
-       reg = nvkm_falcon_rd32(falcon, 0xc08);
-       falcon->debug = (reg >> 20) & 0x1;
+       switch (subdev->index) {
+       case NVKM_ENGINE_GR:
+               debug_reg = 0x0;
+               break;
+       case NVKM_SUBDEV_PMU:
+               debug_reg = 0xc08;
+               break;
+       case NVKM_ENGINE_NVDEC:
+               debug_reg = 0xd00;
+               break;
+       case NVKM_ENGINE_SEC2:
+               debug_reg = 0x408;
+               break;
+       default:
+               nvkm_warn(subdev, "unsupported falcon %s!\n",
+                         nvkm_subdev_name[subdev->index]);
+               debug_reg = 0;
+               break;
+       }
+
+       if (debug_reg) {
+               u32 val = nvkm_falcon_rd32(falcon, debug_reg);
+               falcon->debug = (val >> 20) & 0x1;
+       }
 }
 
 void