drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI

The PCH transcoder registers are only 12 bits wide for the hdisplay
and hblank_start values. On HSW/BDW the CPU side registers are 13
bits wide. intel_mode_valid() only checks against the higher limit
(since we don't know where the mode is to be used), so an extra
check is required against the FDI limits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-3-ville.syrjala@linux.intel.com
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index a1ddd9f62bb8f6d6eaedcf2ec61f66af4e89ff67..0c6bf82bb059a87e1b6ce96e1412bb0aa60f92f3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -337,6 +337,10 @@ intel_crt_mode_valid(struct drm_connector *connector,
            (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
                return MODE_CLOCK_HIGH;
 
+       /* HSW/BDW FDI limited to 4k */
+       if (mode->hdisplay > 4096)
+               return MODE_H_ILLEGAL;
+
        return MODE_OK;
 }
 
@@ -379,6 +383,11 @@ static bool hsw_crt_compute_config(struct intel_encoder *encoder,
        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
                return false;
 
+       /* HSW/BDW FDI limited to 4k */
+       if (adjusted_mode->crtc_hdisplay > 4096 ||
+           adjusted_mode->crtc_hblank_start > 4096)
+               return false;
+
        pipe_config->has_pch_encoder = true;
 
        /* LPT FDI RX only supports 8bpc. */