/* ide-pci.c */
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
int secondary_ide_enabled);
-void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
- qemu_irq *pic);
-void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
- qemu_irq *pic);
+void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
+void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
/* ide-macio.c */
int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
-void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
- qemu_irq *pic)
+void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
PCIIDEState *d;
uint8_t *pci_conf;
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
-void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn,
- qemu_irq *pic)
+void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
PCIIDEState *d;
uint8_t *pci_conf;
pci_register_bar((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
- /*
- * These should call isa_reserve_irq() instead when MIPS supports it
- */
- ide_init2(&d->bus[0], hd_table[0], hd_table[1], pic[14]);
- ide_init2(&d->bus[1], hd_table[2], hd_table[3], pic[15]);
+ ide_init2(&d->bus[0], hd_table[0], hd_table[1], isa_reserve_irq(14));
+ ide_init2(&d->bus[1], hd_table[2], hd_table[3], isa_reserve_irq(15));
ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
ide_init_ioport(&d->bus[1], 0x170, 0x376);
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
+ ISADevice *isa_dev;
CPUState *env;
RTCState *rtc_state;
fdctrl_t *floppy_controller;
}
piix4_devfn = piix4_init(pci_bus, 80);
- pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1, i8259);
+ isa_bus_irqs(i8259);
+ pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
- smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, i8259[9]);
+ smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_reserve_irq(9));
eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
for (i = 0; i < 8; i++) {
/* TODO: Populate SPD eeprom data. */
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
qdev_init(eeprom);
}
- pit = pit_init(0x40, i8259[0]);
+ pit = pit_init(0x40, isa_reserve_irq(0));
DMA_init(0);
/* Super I/O */
- i8042_init(i8259[1], i8259[12], 0x60);
- rtc_state = rtc_init(0x70, i8259[8], 2000);
- serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
- serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
+ isa_dev = isa_create_simple("i8042", 0x60, 0x64, 1, 12);
+
+ rtc_state = rtc_init(0x70, isa_reserve_irq(8), 2000);
+ serial_init(0x3f8, isa_reserve_irq(4), 115200, serial_hds[0]);
+ serial_init(0x2f8, isa_reserve_irq(3), 115200, serial_hds[1]);
if (parallel_hds[0])
- parallel_init(0x378, i8259[7], parallel_hds[0]);
+ parallel_init(0x378, isa_reserve_irq(7), parallel_hds[0]);
for(i = 0; i < MAX_FD; i++) {
dinfo = drive_get(IF_FLOPPY, 0, i);
fd[i] = dinfo ? dinfo->bdrv : NULL;
}
if (pci_enabled) {
- pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, isa_irq);
+ pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
} else {
for(i = 0; i < MAX_IDE_BUS; i++) {
isa_ide_init(ide_iobase[i], ide_iobase2[i],
{
uint8_t *pci_conf;
+ isa_bus_new(&d->qdev);
register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
pci_conf = d->config;