pinctrl: intel: Disable input and output buffer when switching to GPIO

It's possible scenario that pin has been in different mode, while
the respective GPIO register has a leftover output buffer enabled.
In such case when we request GPIO it will switch to GPIO mode, and
thus to output with unknown value, followed by switching to input
mode. This can produce a glitch on the pin.

Disable input and output buffer when switching to GPIO to avoid
potential glitches.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 6a274e20d92690a4bb2737b18e47651c41df44a5..9df5a0c0d416f769780005178978cdd913339eda 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -435,11 +435,20 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 {
        u32 value;
 
+       value = readl(padcfg0);
+
        /* Put the pad into GPIO mode */
-       value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
+       value &= ~PADCFG0_PMODE_MASK;
+       value |= PADCFG0_PMODE_GPIO;
+
+       /* Disable input and output buffers */
+       value &= ~PADCFG0_GPIORXDIS;
+       value &= ~PADCFG0_GPIOTXDIS;
+
        /* Disable SCI/SMI/NMI generation */
        value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
        value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
+
        writel(value, padcfg0);
 }
 
@@ -1036,6 +1045,9 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
 
        intel_gpio_set_gpio_mode(reg);
 
+       /* Disable TX buffer and enable RX (this will be input) */
+       __intel_gpio_set_direction(reg, true);
+
        value = readl(reg);
 
        value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);