drm/i915/lrc: User PXP contexts requires runalone bit in lrc

On Meteorlake onwards, HW specs require that all user contexts that
run on render or compute engines and require PXP must enforce
run-alone bit in lrc. Add this enforcement for protected contexts.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Vivaik Balasubrawmanian <vivaik.balasubrawmanian@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230917211933.1407559-4-alan.previn.teres.alexis@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 6b9d9f8376692ff55c52ad142091e2a3fd0923cb..fdd4ddd3a978a231afbcd0e217265178144cf401 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -177,6 +177,7 @@
 #define   CTX_CTRL_RS_CTX_ENABLE               REG_BIT(1)
 #define          CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT      REG_BIT(2)
 #define          CTX_CTRL_INHIBIT_SYN_CTX_SWITCH       REG_BIT(3)
+#define          GEN12_CTX_CTRL_RUNALONE_MODE          REG_BIT(7)
 #define          GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE     REG_BIT(8)
 #define RING_CTX_SR_CTL(base)                  _MMIO((base) + 0x244)
 #define RING_SEMA_WAIT_POLL(base)              _MMIO((base) + 0x24c)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 147b6f44ad56d98bfccdd9e7ba40f0353b379ece..eaf66d90316655ce0d43ab66dc023ee2950e24e2 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -845,6 +845,27 @@ lrc_setup_indirect_ctx(u32 *regs,
                lrc_ring_indirect_offset_default(engine) << 6;
 }
 
+static bool ctx_needs_runalone(const struct intel_context *ce)
+{
+       struct i915_gem_context *gem_ctx;
+       bool ctx_is_protected = false;
+
+       /*
+        * On MTL and newer platforms, protected contexts require setting
+        * the LRC run-alone bit or else the encryption will not happen.
+        */
+       if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
+           (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) {
+               rcu_read_lock();
+               gem_ctx = rcu_dereference(ce->gem_context);
+               if (gem_ctx)
+                       ctx_is_protected = gem_ctx->uses_protected_content;
+               rcu_read_unlock();
+       }
+
+       return ctx_is_protected;
+}
+
 static void init_common_regs(u32 * const regs,
                             const struct intel_context *ce,
                             const struct intel_engine_cs *engine,
@@ -860,6 +881,8 @@ static void init_common_regs(u32 * const regs,
        if (GRAPHICS_VER(engine->i915) < 11)
                ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
                                           CTX_CTRL_RS_CTX_ENABLE);
+       if (ctx_needs_runalone(ce))
+               ctl |= _MASKED_BIT_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE);
        regs[CTX_CONTEXT_CONTROL] = ctl;
 
        regs[CTX_TIMESTAMP] = ce->stats.runtime.last;