#define ENV_OFFSET offsetof(CRISCPU, env)
void cris_cpu_do_interrupt(CPUState *cpu);
+void crisv10_cpu_do_interrupt(CPUState *cpu);
#endif
static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 8;
+ cc->do_interrupt = crisv10_cpu_do_interrupt;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
+ cc->do_interrupt = crisv10_cpu_do_interrupt;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 10;
+ cc->do_interrupt = crisv10_cpu_do_interrupt;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
{
+ CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 11;
+ cc->do_interrupt = crisv10_cpu_do_interrupt;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
env->pregs[PR_ERP] = env->pc;
}
+void crisv10_cpu_do_interrupt(CPUState *cs)
+{
+ cris_cpu_do_interrupt(cs);
+}
+
int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
int mmu_idx)
{
return r;
}
-static void do_interruptv10(CPUCRISState *env)
+void crisv10_cpu_do_interrupt(CPUState *cs)
{
- D(CPUState *cs = CPU(cris_env_get_cpu(env)));
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
CPUCRISState *env = &cpu->env;
int ex_vec = -1;
- if (env->pregs[PR_VR] < 32) {
- return do_interruptv10(env);
- }
-
D_LOG("exception index=%d interrupt_req=%d\n",
env->exception_index,
cs->interrupt_request);