void op_mfc0_ebase (void)
{
- T0 = (int32_t)env->CP0_EBase;
+ T0 = env->CP0_EBase;
RETURN();
}
{
/* vectored interrupts not implemented */
/* Multi-CPU not implemented */
- env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
+ env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
RETURN();
}
RETURN();
}
-void op_dmfc0_ebase (void)
-{
- T0 = env->CP0_EBase;
- RETURN();
-}
-
void op_dmfc0_lladdr (void)
{
T0 = env->CP0_LLAddr >> 4;
RETURN();
}
-void op_dmtc0_ebase (void)
-{
- /* vectored interrupts not implemented */
- /* Multi-CPU not implemented */
- /* XXX: 64bit addressing broken */
- env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
- RETURN();
-}
-
void op_dmtc0_watchlo0 (void)
{
env->CP0_WatchLo = T0;
rn = "PRid";
break;
case 1:
- gen_op_dmfc0_ebase();
+ gen_op_mfc0_ebase();
rn = "EBase";
break;
default:
rn = "PRid";
break;
case 1:
- gen_op_dmtc0_ebase();
+ gen_op_mtc0_ebase();
rn = "EBase";
break;
default:
#endif
env->CP0_Wired = 0;
/* SMP not implemented */
- env->CP0_EBase = (int32_t)0x80000000;
+ env->CP0_EBase = 0x80000000;
env->CP0_Config0 = MIPS_CONFIG0;
env->CP0_Config1 = MIPS_CONFIG1;
env->CP0_Config2 = MIPS_CONFIG2;