target-sh4: implement negc using TCG

Using setcond it's now possible to generate a relatively short negc
instruction in TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 4e595c87f88679f8a1f95a112ce744c27a139bc1..2e527684142795f1bd06e98db13dd7bea5776d54 100644 (file)
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -17,7 +17,6 @@ DEF_HELPER_2(addv, i32, i32, i32)
 DEF_HELPER_2(addc, i32, i32, i32)
 DEF_HELPER_2(subv, i32, i32, i32)
 DEF_HELPER_2(subc, i32, i32, i32)
-DEF_HELPER_1(negc, i32, i32)
 DEF_HELPER_2(div1, i32, i32, i32)
 DEF_HELPER_2(macl, void, i32, i32)
 DEF_HELPER_2(macw, void, i32, i32)

diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 9d7652f3c7570fb1a677a659230e0f687802f541..30f98422957d747e67bff7d063602496cca94c44 100644 (file)
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -379,21 +379,6 @@ void helper_macw(uint32_t arg0, uint32_t arg1)
     }
 }
 
-uint32_t helper_negc(uint32_t arg)
-{
-    uint32_t temp;
-
-    temp = -arg;
-    arg = temp - (env->sr & SR_T);
-    if (0 < temp)
-       env->sr |= SR_T;
-    else
-       env->sr &= ~SR_T;
-    if (temp < arg)
-       env->sr |= SR_T;
-    return arg;
-}
-
 uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
 {
     uint32_t tmp0, tmp1;

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 743d76a5758bc9b75cd0d1070cd2850affb975b7..35573be5ff2b9425fb4be50ef5d07ff096289f9a 100644 (file)
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -952,7 +952,21 @@ static void _decode_opc(DisasContext * ctx)
        tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
        return;
     case 0x600a:               /* negc Rm,Rn */
-       gen_helper_negc(REG(B11_8), REG(B7_4));
+        {
+           TCGv t0, t1;
+            t0 = tcg_temp_new();
+            tcg_gen_neg_i32(t0, REG(B7_4));
+            t1 = tcg_temp_new();
+            tcg_gen_andi_i32(t1, cpu_sr, SR_T);
+            tcg_gen_sub_i32(REG(B11_8), t0, t1);
+            tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
+            tcg_gen_setcond_i32(TCG_COND_GE, t1, REG(B11_8), t0);
+            tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+            tcg_gen_setcondi_i32(TCG_COND_GE, t1, t0, 0);
+            tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
+            tcg_temp_free(t0);
+            tcg_temp_free(t1);
+        }
        return;
     case 0x6007:               /* not Rm,Rn */
        tcg_gen_not_i32(REG(B11_8), REG(B7_4));