platform/x86: pmc_atom: Fix SLP_TYPx bitfield mask

BugLink: https://bugs.launchpad.net/bugs/1991840
[ Upstream commit 0a90ed8d0cfa29735a221eba14d9cb6c735d35b6 ]

On Intel hardware the SLP_TYPx bitfield occupies bits 10-12 as per ACPI
specification (see Table 4.13 "PM1 Control Registers Fixed Hardware
Feature Control Bits" for the details).

Fix the mask and other related definitions accordingly.

Fixes: 93e5eadd1f6e ("x86/platform: New Intel Atom SOC power management controller driver")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220801113734.36131-1-andriy.shevchenko@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/platform/x86/pmc_atom.c b/drivers/platform/x86/pmc_atom.c
index a9d2a4b98e57022ec5deadb0ecea5f63c4c33823..4b0739f95f8b93aa00cea2e553da870cde0e2570 100644 (file)
--- a/drivers/platform/x86/pmc_atom.c
+++ b/drivers/platform/x86/pmc_atom.c
@@ -244,7 +244,7 @@ static void pmc_power_off(void)
        pm1_cnt_port = acpi_base_addr + PM1_CNT;
 
        pm1_cnt_value = inl(pm1_cnt_port);
-       pm1_cnt_value &= SLEEP_TYPE_MASK;
+       pm1_cnt_value &= ~SLEEP_TYPE_MASK;
        pm1_cnt_value |= SLEEP_TYPE_S5;
        pm1_cnt_value |= SLEEP_ENABLE;
 

diff --git a/include/linux/platform_data/x86/pmc_atom.h b/include/linux/platform_data/x86/pmc_atom.h
index 022bcea9edec5ba8b1c333331746e1532d393917..99a9b09dc839d10c8adb3ff545eda2157330f48f 100644 (file)
--- a/include/linux/platform_data/x86/pmc_atom.h
+++ b/include/linux/platform_data/x86/pmc_atom.h
@@ -7,6 +7,8 @@
 #ifndef PMC_ATOM_H
 #define PMC_ATOM_H
 
+#include <linux/bits.h>
+
 /* ValleyView Power Control Unit PCI Device ID */
 #define        PCI_DEVICE_ID_VLV_PMC   0x0F1C
 /* CherryTrail Power Control Unit PCI Device ID */
@@ -139,9 +141,9 @@
 #define        ACPI_MMIO_REG_LEN       0x100
 
 #define        PM1_CNT                 0x4
-#define        SLEEP_TYPE_MASK         0xFFFFECFF
+#define        SLEEP_TYPE_MASK         GENMASK(12, 10)
 #define        SLEEP_TYPE_S5           0x1C00
-#define        SLEEP_ENABLE            0x2000
+#define        SLEEP_ENABLE            BIT(13)
 
 extern int pmc_atom_read(int offset, u32 *value);
 extern int pmc_atom_write(int offset, u32 value);