drm/radeon/kms: fix vram start calculation on ontario (v2)

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 522d29b37007a54abfdf8df8c1948235ccb9b603..f7d7477daffbb30ba8767da2226a77044f095759 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1134,6 +1134,12 @@ static void evergreen_mc_program(struct radeon_device *rdev)
                        rdev->mc.vram_end >> 12);
        }
        WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+       if (rdev->flags & RADEON_IS_IGP) {
+               tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
+               tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
+               tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
+               WREG32(MC_FUS_VM_FB_OFFSET, tmp);
+       }
        tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
        tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
        WREG32(MC_VM_FB_LOCATION, tmp);

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 87fcaba7669582397147c5e3232fb83b58d0e99e..5b869ce8691748d7dc1e3676381bb23f67391a8e 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -202,6 +202,7 @@
 #define        MC_VM_AGP_BOT                                   0x202C
 #define        MC_VM_AGP_BASE                                  0x2030
 #define        MC_VM_FB_LOCATION                               0x2024
+#define        MC_FUS_VM_FB_OFFSET                             0x2898
 #define        MC_VM_MB_L1_TLB0_CNTL                           0x2234
 #define        MC_VM_MB_L1_TLB1_CNTL                           0x2238
 #define        MC_VM_MB_L1_TLB2_CNTL                           0x223C

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 7c2e0b19a558a5653021b59979a796aee9f059a5..645aa1fd76111ffdb2f2f3e22426cb6cb098fd6e 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -271,12 +271,6 @@ static void rv770_mc_program(struct radeon_device *rdev)
                        rdev->mc.vram_end >> 12);
        }
        WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
-       if (rdev->flags & RADEON_IS_IGP) {
-               tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
-               tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
-               tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
-               WREG32(MC_FUS_VM_FB_OFFSET, tmp);
-       }
        tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
        tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
        WREG32(MC_VM_FB_LOCATION, tmp);
@@ -1074,12 +1068,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
                                mc->mc_vram_size >> 20, mc->vram_start,
                                mc->vram_end, mc->real_vram_size >> 20);
        } else {
-               u64 base = 0;
-               if (rdev->flags & RADEON_IS_IGP) {
-                       base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
-                       base |= RREG32(MC_FUS_VM_FB_OFFSET) & 0x00F00000;
-               }
-               radeon_vram_location(rdev, &rdev->mc, base);
+               radeon_vram_location(rdev, &rdev->mc, 0);
                rdev->mc.gtt_base_align = 0;
                radeon_gtt_location(rdev, mc);
        }

diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 98f9ad256d3d13337b198288e8b32bd4f968306e..fc77e1e1a1799a13c1b5a7f20e13a52e62205556 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -158,7 +158,6 @@
 #define        MC_VM_AGP_BOT                                   0x202C
 #define        MC_VM_AGP_BASE                                  0x2030
 #define        MC_VM_FB_LOCATION                               0x2024
-#define        MC_FUS_VM_FB_OFFSET                             0x2898
 #define        MC_VM_MB_L1_TLB0_CNTL                           0x2234
 #define        MC_VM_MB_L1_TLB1_CNTL                           0x2238
 #define        MC_VM_MB_L1_TLB2_CNTL                           0x223C