net: phy: make use of new MMD accessors

Make use of the new MMD accessors.

v2:
- fix SoB

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 8a8d9f606b3eb2529d89bc2e66a6cf630c3e9deb..fc09c5c1a4de363efa8918e1f13e827270c7184e 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -127,17 +127,13 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
 {
        struct dp83867_private *dp83867 =
                (struct dp83867_private *)phydev->priv;
-       u16 val;
-
-       val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 
        if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
-               val |= DP83867_CFG4_PORT_MIRROR_EN;
+               phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
+                                DP83867_CFG4_PORT_MIRROR_EN);
        else
-               val &= ~DP83867_CFG4_PORT_MIRROR_EN;
-
-       phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
-
+               phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
+                                  DP83867_CFG4_PORT_MIRROR_EN);
        return 0;
 }
 
@@ -222,11 +218,9 @@ static int dp83867_config_init(struct phy_device *phydev)
        }
 
        /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
-       if (dp83867->rxctrl_strap_quirk) {
-               val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
-               val &= ~BIT(7);
-               phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
-       }
+       if (dp83867->rxctrl_strap_quirk)
+               phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
+                                  BIT(7));
 
        if (phy_interface_is_rgmii(phydev)) {
                val = phy_read(phydev, MII_DP83867_PHYCTRL);
@@ -275,17 +269,11 @@ static int dp83867_config_init(struct phy_device *phydev)
                phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
                              delay);
 
-               if (dp83867->io_impedance >= 0) {
-                       val = phy_read_mmd(phydev, DP83867_DEVADDR,
-                                          DP83867_IO_MUX_CFG);
-
-                       val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
-                       val |= dp83867->io_impedance &
-                              DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
-
-                       phy_write_mmd(phydev, DP83867_DEVADDR,
-                                     DP83867_IO_MUX_CFG, val);
-               }
+               if (dp83867->io_impedance >= 0)
+                       phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
+                                      DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
+                                      dp83867->io_impedance &
+                                      DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
        }
 
        /* Enable Interrupt output INT_OE in CFG3 register */
@@ -299,12 +287,11 @@ static int dp83867_config_init(struct phy_device *phydev)
                dp83867_config_port_mirroring(phydev);
 
        /* Clock output selection if muxing property is set */
-       if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
-               val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
-               val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
-               val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
-               phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
-       }
+       if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
+               phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
+                              DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
+                              dp83867->clk_output_sel <<
+                              DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 
        return 0;
 }

diff --git a/drivers/net/phy/dp83tc811.c b/drivers/net/phy/dp83tc811.c
index da13356999e5736578a6ff0bcaba7ac6222d6130..e9704af1d239b8650edc56a40f6d12804371116e 100644 (file)
--- a/drivers/net/phy/dp83tc811.c
+++ b/drivers/net/phy/dp83tc811.c
@@ -144,11 +144,8 @@ static int dp83811_set_wol(struct phy_device *phydev,
                phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
                              value);
        } else {
-               value = phy_read_mmd(phydev, DP83811_DEVADDR,
-                                    MII_DP83811_WOL_CFG);
-               value &= ~DP83811_WOL_EN;
-               phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
-                             value);
+               phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
+                                  DP83811_WOL_EN);
        }
 
        return 0;
@@ -328,14 +325,10 @@ static int dp83811_suspend(struct phy_device *phydev)
 
 static int dp83811_resume(struct phy_device *phydev)
 {
-       int value;
-
        genphy_resume(phydev);
 
-       value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
-
-       phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, value |
-                     DP83811_WOL_CLR_INDICATION);
+       phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
+                        DP83811_WOL_CLR_INDICATION);
 
        return 0;
 }

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 38cfc923a88a56b9ef3c8fd82e83fb2912ff3470..5531f9cabc63f0b977204eb18be415e2f85fbcac 100644 (file)
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -58,24 +58,6 @@ struct mv3310_priv {
        char *hwmon_name;
 };
 
-static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
-                        u16 mask, u16 bits)
-{
-       int old, val, ret;
-
-       old = phy_read_mmd(phydev, devad, reg);
-       if (old < 0)
-               return old;
-
-       val = (old & ~mask) | (bits & mask);
-       if (val == old)
-               return 0;
-
-       ret = phy_write_mmd(phydev, devad, reg, val);
-
-       return ret < 0 ? ret : 1;
-}
-
 #ifdef CONFIG_HWMON
 static umode_t mv3310_hwmon_is_visible(const void *data,
                                       enum hwmon_sensor_types type,
@@ -159,8 +141,8 @@ static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
                return ret;
 
        val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
-       ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
-                           MV_V2_TEMP_CTRL_MASK, val);
+       ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
+                            MV_V2_TEMP_CTRL_MASK, val);
 
        return ret < 0 ? ret : 0;
 }
@@ -363,18 +345,18 @@ static int mv3310_config_aneg(struct phy_device *phydev)
        linkmode_and(phydev->advertising, phydev->advertising,
                     phydev->supported);
 
-       ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
-                           ADVERTISE_ALL | ADVERTISE_100BASE4 |
-                           ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
-                           linkmode_adv_to_mii_adv_t(phydev->advertising));
+       ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
+                            ADVERTISE_ALL | ADVERTISE_100BASE4 |
+                            ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
+                            linkmode_adv_to_mii_adv_t(phydev->advertising));
        if (ret < 0)
                return ret;
        if (ret > 0)
                changed = true;
 
        reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
-       ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
-                           ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
+       ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
+                            ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
        if (ret < 0)
                return ret;
        if (ret > 0)
@@ -387,8 +369,8 @@ static int mv3310_config_aneg(struct phy_device *phydev)
        else
                reg = 0;
 
-       ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
-                           MDIO_AN_10GBT_CTRL_ADV10G, reg);
+       ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
+                            MDIO_AN_10GBT_CTRL_ADV10G, reg);
        if (ret < 0)
                return ret;
        if (ret > 0)

diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
index 03af927fa5ad46f89693e49f0640b387bc596a8f..519866679c91e538943ac3e9dfd0228e25c47ac0 100644 (file)
--- a/drivers/net/phy/phy-c45.c
+++ b/drivers/net/phy/phy-c45.c
@@ -75,15 +75,9 @@ EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
  */
 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
 {
-       int val;
-
-       val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
-       if (val < 0)
-               return val;
-
-       val &= ~(MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 
-       return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);
+       return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
+                                 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 }
 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
 
@@ -97,15 +91,8 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
  */
 int genphy_c45_restart_aneg(struct phy_device *phydev)
 {
-       int val;
-
-       val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
-       if (val < 0)
-               return val;
-
-       val |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
-
-       return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);
+       return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
+                               MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 }
 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
 

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index d12aa512b7f582b140a6e7db5cea16a27b451d17..89ead29cec6816bbce280aa2e9e2a0f3f8115339 100644 (file)
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1060,17 +1060,12 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
                if (!phy_check_valid(phydev->speed, phydev->duplex, common))
                        goto eee_exit_err;
 
-               if (clk_stop_enable) {
+               if (clk_stop_enable)
                        /* Configure the PHY to stop receiving xMII
                         * clock while it is signaling LPI.
                         */
-                       int val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
-                       if (val < 0)
-                               return val;
-
-                       val |= MDIO_PCS_CTRL1_CLKSTOP_EN;
-                       phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, val);
-               }
+                       phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
+                                        MDIO_PCS_CTRL1_CLKSTOP_EN);
 
                return 0; /* EEE supported */
        }