drm/amd/display: Don't share clk source between DP and HDMI

BugLink: https://bugs.launchpad.net/bugs/1835972
commit 3e27e10e2ecee0d3a0083f8ae76354ac9c6ad15c upstream.

[why]
Prevent clock source sharing between HDMI and DP connectors.
DP shouldn't be sharing its ref clock with phy clock,
which caused an issue of older ASICS booting up with multiple
diplays plugged in.

[how]
Add an extra check that would prevent HDMI and DP sharing clk.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 078161b42b3e37a1ec065d7efcaf14489bd92a3c..28533298f6060bea81a86d6ff5a4827235fc5632 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -325,6 +325,9 @@ bool resource_are_streams_timing_synchronizable(
                                != stream2->timing.pix_clk_khz)
                return false;
 
+       if (stream1->clamping.c_depth != stream2->clamping.c_depth)
+               return false;
+
        if (stream1->phy_pix_clk != stream2->phy_pix_clk
                        && (!dc_is_dp_signal(stream1->signal)
                        || !dc_is_dp_signal(stream2->signal)))
@@ -332,6 +335,20 @@ bool resource_are_streams_timing_synchronizable(
 
        return true;
 }
+static bool is_dp_and_hdmi_sharable(
+               struct dc_stream_state *stream1,
+               struct dc_stream_state *stream2)
+{
+       if (stream1->ctx->dc->caps.disable_dp_clk_share)
+               return false;
+
+       if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
+           stream2->clamping.c_depth != COLOR_DEPTH_888)
+       return false;
+
+       return true;
+
+}
 
 static bool is_sharable_clk_src(
        const struct pipe_ctx *pipe_with_clk_src,
@@ -343,7 +360,10 @@ static bool is_sharable_clk_src(
        if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
                return false;
 
-       if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
+       if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
+               (dc_is_dp_signal(pipe->stream->signal) &&
+               !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
+                                    pipe->stream)))
                return false;
 
        if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9d8f4a55c74e98c9c6c1e0a424bf00b00397a9b7..8d830e5f894370b21d191b352ed5fc1ef2fc5607 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -60,6 +60,7 @@ struct dc_caps {
        unsigned int max_video_width;
        bool dcc_const_color;
        bool dynamic_audio;
+       bool disable_dp_clk_share;
 };
 
 struct dc_dcc_surface_param {

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3e01f445539c2b0e8f34f8f7312585bf8f0575c7..515e76cb1743cb0baf07af4a7005d39e4edede54 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -865,7 +865,7 @@ static bool construct(
        dc->caps.max_downscale_ratio = 200;
        dc->caps.i2c_speed_in_khz = 40;
        dc->caps.max_cursor_size = 128;
-
+       dc->caps.disable_dp_clk_share = true;
        for (i = 0; i < pool->base.pipe_count; i++) {
                pool->base.timing_generators[i] =
                        dce100_timing_generator_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 9c18efd3446f502b1669a3f8fd69346cbf44c31b..9e0336d4f10f6c4a67b105ad3b5727765b6b029c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -900,6 +900,7 @@ static bool dce80_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+       dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
                        &res_create_funcs))
@@ -1064,6 +1065,7 @@ static bool dce81_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+       dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
                        &res_create_funcs))
@@ -1224,6 +1226,7 @@ static bool dce83_construct(
        }
 
        dc->caps.max_planes =  pool->base.pipe_count;
+       dc->caps.disable_dp_clk_share = true;
 
        if (!resource_construct(num_virtual_links, dc, &pool->base,
                        &res_create_funcs))