drm/nouveau: remove subchannel names from places where it doesn't matter

These are FIFO methods, it doesn't matter what subchannel is being used.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 0df21752d2743fc654d390eb5f522deb2d044628..eaf9872f9ee2c91e8bb6854c2136a39a2f7bea24 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -1763,13 +1763,26 @@ nv44_graph_class(struct drm_device *dev)
 #define NV_MEM_TYPE_VM 0x7f
 #define NV_MEM_COMP_VM 0x03
 
+/* FIFO methods */
+#define NV01_SUBCHAN_OBJECT                                          0x00000000
+#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH                          0x00000010
+#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW                           0x00000014
+#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE                              0x00000018
+#define NV84_SUBCHAN_SEMAPHORE_TRIGGER                               0x0000001c
+#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL                 0x00000001
+#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG                    0x00000002
+#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL                0x00000004
+#define NV84_SUBCHAN_NOTIFY_INTR                                     0x00000020
+#define NV84_SUBCHAN_WRCACHE_FLUSH                                   0x00000024
+#define NV10_SUBCHAN_REF_CNT                                         0x00000050
+#define NV11_SUBCHAN_DMA_SEMAPHORE                                   0x00000060
+#define NV11_SUBCHAN_SEMAPHORE_OFFSET                                0x00000064
+#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE                               0x00000068
+#define NV11_SUBCHAN_SEMAPHORE_RELEASE                               0x0000006c
+#define NV40_SUBCHAN_YIELD                                           0x00000080
+
 /* NV_SW object class */
 #define NV_SW                                                        0x0000506e
-#define NV_SW_DMA_SEMAPHORE                                          0x00000060
-#define NV_SW_SEMAPHORE_OFFSET                                       0x00000064
-#define NV_SW_SEMAPHORE_ACQUIRE                                      0x00000068
-#define NV_SW_SEMAPHORE_RELEASE                                      0x0000006c
-#define NV_SW_YIELD                                                  0x00000080
 #define NV_SW_DMA_VBLSEM                                             0x0000018c
 #define NV_SW_VBLSEM_OFFSET                                          0x00000400
 #define NV_SW_VBLSEM_RELEASE_VALUE                                   0x00000404

diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 2f6daae68b9d7e24830bb9f2cc5e5af09cbe4f8b..f676ecd3fd3c576c0b86c2990b934aa344671d2c 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -165,9 +165,9 @@ nouveau_fence_emit(struct nouveau_fence *fence)
 
        if (USE_REFCNT(dev)) {
                if (dev_priv->card_type < NV_C0)
-                       BEGIN_RING(chan, NvSubSw, 0x0050, 1);
+                       BEGIN_RING(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
                else
-                       BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0050, 1);
+                       BEGIN_NVC0(chan, 2, 0, NV10_SUBCHAN_REF_CNT, 1);
        } else {
                BEGIN_RING(chan, NvSubSw, 0x0150, 1);
        }
@@ -344,7 +344,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
                if (ret)
                        return ret;
 
-               BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 3);
+               BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 3);
                OUT_RING  (chan, NvSema);
                OUT_RING  (chan, offset);
                OUT_RING  (chan, 1);
@@ -354,9 +354,9 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
                if (ret)
                        return ret;
 
-               BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
+               BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
                OUT_RING  (chan, chan->vram_handle);
-               BEGIN_RING(chan, NvSubSw, 0x0010, 4);
+               BEGIN_RING(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
                OUT_RING  (chan, upper_32_bits(offset));
                OUT_RING  (chan, lower_32_bits(offset));
                OUT_RING  (chan, 1);
@@ -366,7 +366,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
                if (ret)
                        return ret;
 
-               BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
+               BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
                OUT_RING  (chan, upper_32_bits(offset));
                OUT_RING  (chan, lower_32_bits(offset));
                OUT_RING  (chan, 1);
@@ -397,10 +397,10 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
                if (ret)
                        return ret;
 
-               BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 2);
+               BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
                OUT_RING  (chan, NvSema);
                OUT_RING  (chan, offset);
-               BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1);
+               BEGIN_RING(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
                OUT_RING  (chan, 1);
        } else
        if (dev_priv->chipset < 0xc0) {
@@ -408,9 +408,9 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
                if (ret)
                        return ret;
 
-               BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1);
+               BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
                OUT_RING  (chan, chan->vram_handle);
-               BEGIN_RING(chan, NvSubSw, 0x0010, 4);
+               BEGIN_RING(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
                OUT_RING  (chan, upper_32_bits(offset));
                OUT_RING  (chan, lower_32_bits(offset));
                OUT_RING  (chan, 1);
@@ -420,7 +420,7 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
                if (ret)
                        return ret;
 
-               BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
+               BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
                OUT_RING  (chan, upper_32_bits(offset));
                OUT_RING  (chan, lower_32_bits(offset));
                OUT_RING  (chan, 1);
@@ -510,7 +510,7 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
                if (ret)
                        return ret;
 
-               BEGIN_RING(chan, NvSubSw, 0, 1);
+               BEGIN_RING(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1);
                OUT_RING  (chan, NvSw);
                FIRE_RING (chan);
        }

diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 0e47a898f415335f72e68ba6de7048a1ad3bba99..8b78b9cfa3839ba048090a981fca6bd4c29bb3e0 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -474,15 +474,15 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                }
 
                if (dev_priv->chipset < 0xc0) {
-                       BEGIN_RING(chan, NvSubSw, 0x0060, 2);
+                       BEGIN_RING(chan, 0, 0x0060, 2);
                        OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
                        OUT_RING  (chan, dispc->sem.offset);
-                       BEGIN_RING(chan, NvSubSw, 0x006c, 1);
+                       BEGIN_RING(chan, 0, 0x006c, 1);
                        OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
-                       BEGIN_RING(chan, NvSubSw, 0x0064, 2);
+                       BEGIN_RING(chan, 0, 0x0064, 2);
                        OUT_RING  (chan, dispc->sem.offset ^ 0x10);
                        OUT_RING  (chan, 0x74b1e000);
-                       BEGIN_RING(chan, NvSubSw, 0x0060, 1);
+                       BEGIN_RING(chan, 0, 0x0060, 1);
                        if (dev_priv->chipset < 0x84)
                                OUT_RING  (chan, NvSema);
                        else
@@ -490,12 +490,12 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                } else {
                        u64 offset = chan->dispc_vma[nv_crtc->index].offset;
                        offset += dispc->sem.offset;
-                       BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
+                       BEGIN_NVC0(chan, 2, 0, 0x0010, 4);
                        OUT_RING  (chan, upper_32_bits(offset));
                        OUT_RING  (chan, lower_32_bits(offset));
                        OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
                        OUT_RING  (chan, 0x1002);
-                       BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
+                       BEGIN_NVC0(chan, 2, 0, 0x0010, 4);
                        OUT_RING  (chan, upper_32_bits(offset));
                        OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
                        OUT_RING  (chan, 0x74b1e000);

diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c
index dfb8a951cbbe3cfe8333cec7001f44d02dd5bf39..5e2b79bdcae0deeb81633695ecc53ad672eb84db 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvd0_display.c
+++ b/drivers/gpu/drm/nouveau/nvd0_display.c
@@ -303,12 +303,12 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                offset  = chan->dispc_vma[nv_crtc->index].offset;
                offset += evo->sem.offset;
 
-               BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
+               BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
                OUT_RING  (chan, upper_32_bits(offset));
                OUT_RING  (chan, lower_32_bits(offset));
                OUT_RING  (chan, 0xf00d0000 | evo->sem.value);
                OUT_RING  (chan, 0x1002);
-               BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
+               BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
                OUT_RING  (chan, upper_32_bits(offset));
                OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
                OUT_RING  (chan, 0x74b1e000);