This bit was originally wrong, the correct value is BIT(1), so fix it.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
#define MVPP2_GMAC_CTRL_1_REG 0x4
-#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(0)
+#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
#define MVPP2_GMAC_PCS_LB_EN_BIT 6
#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)