]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/commitdiff
ARM: shmobile: r8a7791: Add SSI clocks in device tree
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Thu, 19 Dec 2013 15:51:06 +0000 (16:51 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Tue, 24 Dec 2013 14:01:13 +0000 (23:01 +0900)
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7791.dtsi
include/dt-bindings/clock/r8a7791-clock.h

index 19c65509a22d8b10cc48e667fb747bdda0d6ee1e..e92c1f7aedd055a2a409adb3d5f61e15795f804c 100644 (file)
                                "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
                                "i2c2", "i2c1", "i2c0";
                };
+               mstp10_clks: mstp10_clks@e6150998 {
+                       compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+                       clocks = <&p_clk>, <&mstp10_clks R8A7791_CLK_SSI>,
+                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
+                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
+                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
+                                <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>,
+                                <&mstp10_clks R8A7791_CLK_SSI>;
+                       #clock-cells = <1>;
+                       renesas,clock-indices = <
+                               R8A7791_CLK_SSI R8A7791_CLK_SSI9 R8A7791_CLK_SSI8
+                               R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
+                               R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2
+                               R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
+                       >;
+                       clock-output-names =
+                               "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+                               "ssi4", "ssi3", "ssi2", "ssi1", "ssi0";
+               };
                mstp11_clks: mstp11_clks@e615099c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
index 30f82f286e295df3423dd6729ef48918c80683c2..1c8f00d0d88b25f0578bd413def76cbd8067f054 100644 (file)
 #define R8A7791_CLK_I2C1               30
 #define R8A7791_CLK_I2C0               31
 
+/* MSTP10 */
+#define R8A7791_CLK_SSI                        5
+#define R8A7791_CLK_SSI9               6
+#define R8A7791_CLK_SSI8               7
+#define R8A7791_CLK_SSI7               8
+#define R8A7791_CLK_SSI6               9
+#define R8A7791_CLK_SSI5               10
+#define R8A7791_CLK_SSI4               11
+#define R8A7791_CLK_SSI3               12
+#define R8A7791_CLK_SSI2               13
+#define R8A7791_CLK_SSI1               14
+#define R8A7791_CLK_SSI0               15
+
 /* MSTP11 */
 #define R8A7791_CLK_SCIFA3             6
 #define R8A7791_CLK_SCIFA4             7