iommu/arm-smmu: Support SMMUv1 64KB supplement

The 64KB Translation Granule Supplement to the SMMUv1 architecture
allows an SMMUv1 implementation to support 64KB pages for stage 2
translations, using a constrained VMSAv8 descriptor format limited
to 40-bit addresses. Now that we can freely mix and match context
formats, we can actually handle having 4KB pages via an AArch32
context but 64KB pages via an AArch64 context, so plumb it in.

It is assumed that any implementations will have hardware capabilities
matching the format constraints, thus obviating the need for excessive
sanity-checking; this is the case for MMU-401, the only ARM Ltd.
implementation.

CC: Eric Auger <eric.auger@linaro.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index f2ded69feba7dc2fdc62b0b57e545ac2f8696baf..72dea314f9a10b9c51ac3a649304bf9ef5f8c92a 100644 (file)
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -277,7 +277,8 @@ MODULE_PARM_DESC(disable_bypass,
        "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
 
 enum arm_smmu_arch_version {
-       ARM_SMMU_V1 = 1,
+       ARM_SMMU_V1,
+       ARM_SMMU_V1_64K,
        ARM_SMMU_V2,
 };
 
@@ -769,7 +770,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
 
        /* CBAR */
        reg = cfg->cbar;
-       if (smmu->version == ARM_SMMU_V1)
+       if (smmu->version < ARM_SMMU_V2)
                reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 
        /*
@@ -934,7 +935,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
                goto out_unlock;
 
        cfg->cbndx = ret;
-       if (smmu->version == ARM_SMMU_V1) {
+       if (smmu->version < ARM_SMMU_V2) {
                cfg->irptndx = atomic_inc_return(&smmu->irptndx);
                cfg->irptndx %= smmu->num_context_irqs;
        } else {
@@ -1619,7 +1620,8 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
        bool cttw_dt, cttw_reg;
 
        dev_notice(smmu->dev, "probing hardware configuration...\n");
-       dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
+       dev_notice(smmu->dev, "SMMUv%d with:\n",
+                       smmu->version == ARM_SMMU_V2 ? 2 : 1);
 
        /* ID0 */
        id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
@@ -1651,7 +1653,8 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
                return -ENODEV;
        }
 
-       if ((id & ID0_S1TS) && ((smmu->version == 1) || !(id & ID0_ATOSNS))) {
+       if ((id & ID0_S1TS) &&
+               ((smmu->version < ARM_SMMU_V2) || !(id & ID0_ATOSNS))) {
                smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
                dev_notice(smmu->dev, "\taddress translation ops\n");
        }
@@ -1766,8 +1769,10 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
                dev_warn(smmu->dev,
                         "failed to set DMA mask for table walker\n");
 
-       if (smmu->version == ARM_SMMU_V1) {
+       if (smmu->version < ARM_SMMU_V2) {
                smmu->va_size = smmu->ipa_size;
+               if (smmu->version == ARM_SMMU_V1_64K)
+                       smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K;
        } else {
                size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
                smmu->va_size = arm_smmu_id_size_to_bits(size);
@@ -1815,6 +1820,7 @@ static struct arm_smmu_match_data name = { .version = ver, .model = imp }
 
 ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
 ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
+ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
 ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
 ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
 
@@ -1822,7 +1828,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
        { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
        { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
        { .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
-       { .compatible = "arm,mmu-401", .data = &smmu_generic_v1 },
+       { .compatible = "arm,mmu-401", .data = &arm_mmu401 },
        { .compatible = "arm,mmu-500", .data = &arm_mmu500 },
        { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
        { },
@@ -1916,7 +1922,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
 
        parse_driver_options(smmu);
 
-       if (smmu->version > ARM_SMMU_V1 &&
+       if (smmu->version == ARM_SMMU_V2 &&
            smmu->num_context_banks != smmu->num_context_irqs) {
                dev_err(dev,
                        "found only %d context interrupt(s) but %d required\n",