QOM CPUState and X86CPU
* Adoption of CPUClass::disas_set_info() hook
# gpg: Signature made Thu 22 Oct 2015 17:11:24 BST using RSA key ID
3E7E013F
# gpg: Good signature from "Andreas Färber <afaerber@suse.de>"
# gpg: aka "Andreas Färber <afaerber@suse.com>"
* remotes/afaerber/tags/qom-cpu-for-peter:
disas: QOMify alpha specific disas setup
disas: QOMify mips specific disas setup
disas: QOMify sh4 specific disas setup
disas: QOMify lm32 specific disas setup
disas: QOMify sparc specific disas setup
disas: QOMify m68k specific disas setup
disas: QOMify moxie specific disas setup
disas: QOMify s390x specific disas setup
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
s.info.mach = bfd_mach_i386_i386;
}
s.info.print_insn = print_insn_i386;
-#elif defined(TARGET_SPARC)
- s.info.print_insn = print_insn_sparc;
-#ifdef TARGET_SPARC64
- s.info.mach = bfd_mach_sparc_v9b;
-#endif
#elif defined(TARGET_PPC)
if ((flags >> 16) & 1) {
s.info.endian = BFD_ENDIAN_LITTLE;
}
s.info.disassembler_options = (char *)"any";
s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_M68K)
- s.info.print_insn = print_insn_m68k;
-#elif defined(TARGET_MIPS)
-#ifdef TARGET_WORDS_BIGENDIAN
- s.info.print_insn = print_insn_big_mips;
-#else
- s.info.print_insn = print_insn_little_mips;
-#endif
-#elif defined(TARGET_SH4)
- s.info.mach = bfd_mach_sh4;
- s.info.print_insn = print_insn_sh;
-#elif defined(TARGET_ALPHA)
- s.info.mach = bfd_mach_alpha_ev6;
- s.info.print_insn = print_insn_alpha;
-#elif defined(TARGET_S390X)
- s.info.mach = bfd_mach_s390_64;
- s.info.print_insn = print_insn_s390;
-#elif defined(TARGET_MOXIE)
- s.info.mach = bfd_arch_moxie;
- s.info.print_insn = print_insn_moxie;
-#elif defined(TARGET_LM32)
- s.info.mach = bfd_mach_lm32;
- s.info.print_insn = print_insn_lm32;
#endif
if (s.info.print_insn == NULL) {
s.info.print_insn = print_insn_od_target;
s.info.mach = bfd_mach_i386_i386;
}
s.info.print_insn = print_insn_i386;
-#elif defined(TARGET_ALPHA)
- s.info.print_insn = print_insn_alpha;
-#elif defined(TARGET_SPARC)
- s.info.print_insn = print_insn_sparc;
-#ifdef TARGET_SPARC64
- s.info.mach = bfd_mach_sparc_v9b;
-#endif
#elif defined(TARGET_PPC)
if (flags & 0xFFFF) {
/* If we have a precise definition of the instruction set, use it. */
s.info.endian = BFD_ENDIAN_LITTLE;
}
s.info.print_insn = print_insn_ppc;
-#elif defined(TARGET_M68K)
- s.info.print_insn = print_insn_m68k;
-#elif defined(TARGET_MIPS)
-#ifdef TARGET_WORDS_BIGENDIAN
- s.info.print_insn = print_insn_big_mips;
-#else
- s.info.print_insn = print_insn_little_mips;
-#endif
-#elif defined(TARGET_SH4)
- s.info.mach = bfd_mach_sh4;
- s.info.print_insn = print_insn_sh;
-#elif defined(TARGET_S390X)
- s.info.mach = bfd_mach_s390_64;
- s.info.print_insn = print_insn_s390;
-#elif defined(TARGET_MOXIE)
- s.info.mach = bfd_arch_moxie;
- s.info.print_insn = print_insn_moxie;
-#elif defined(TARGET_LM32)
- s.info.mach = bfd_mach_lm32;
- s.info.print_insn = print_insn_lm32;
#endif
if (!s.info.print_insn) {
monitor_printf(mon, "0x" TARGET_FMT_lx
| CPU_INTERRUPT_MCHK);
}
+static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->mach = bfd_mach_alpha_ev6;
+ info->print_insn = print_insn_alpha;
+}
+
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
#endif
+ cc->disas_set_info = alpha_cpu_disas_set_info;
+
cc->gdb_num_core_regs = 67;
/*
tlb_flush(s, 1);
}
+static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->mach = bfd_mach_lm32;
+ info->print_insn = print_insn_lm32;
+}
+
static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = lm32_debug_excp_handler;
+ cc->disas_set_info = lm32_cpu_disas_set_info;
/*
* Reason: lm32_cpu_initfn() calls cpu_exec_init(), which saves
tlb_flush(s, 1);
}
+static void m68k_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->print_insn = print_insn_m68k;
+}
+
/* CPU models */
static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model)
#endif
cc->cpu_exec_enter = m68k_cpu_exec_enter;
cc->cpu_exec_exit = m68k_cpu_exec_exit;
+ cc->disas_set_info = m68k_cpu_disas_set_info;
- dc->vmsd = &vmstate_m68k_cpu;
cc->gdb_num_core_regs = 18;
cc->gdb_core_xml_file = "cf-core.xml";
+ dc->vmsd = &vmstate_m68k_cpu;
+
/*
* Reason: m68k_cpu_initfn() calls cpu_exec_init(), which saves
* the object in cpus -> dangling pointer after final
#endif
}
+static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
+#ifdef TARGET_WORDS_BIGENDIAN
+ info->print_insn = print_insn_big_mips;
+#else
+ info->print_insn = print_insn_little_mips;
+#endif
+}
+
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
#endif
+ cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
tlb_flush(s, 1);
}
+static void moxie_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->mach = bfd_arch_moxie;
+ info->print_insn = print_insn_moxie;
+}
+
static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
#endif
+ cc->disas_set_info = moxie_cpu_disas_set_info;
/*
* Reason: moxie_cpu_initfn() calls cpu_exec_init(), which saves
}
#endif
+static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->mach = bfd_mach_s390_64;
+ info->print_insn = print_insn_s390;
+}
+
static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;
cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
#endif
+ cc->disas_set_info = s390_cpu_disas_set_info;
+
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
cc->gdb_core_xml_file = "s390x-core64.xml";
set_default_nan_mode(1, &env->fp_status);
}
+static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->mach = bfd_mach_sh4;
+ info->print_insn = print_insn_sh;
+}
+
typedef struct SuperHCPUListState {
fprintf_function cpu_fprintf;
FILE *file;
#else
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
- dc->vmsd = &vmstate_sh_cpu;
+ cc->disas_set_info = superh_cpu_disas_set_info;
+
cc->gdb_num_core_regs = 59;
+ dc->vmsd = &vmstate_sh_cpu;
+
/*
* Reason: superh_cpu_initfn() calls cpu_exec_init(), which saves
* the object in cpus -> dangling pointer after final
return false;
}
+static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->print_insn = print_insn_sparc;
+#ifdef TARGET_SPARC64
+ info->mach = bfd_mach_sparc_v9b;
+#endif
+}
+
static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
#endif
+ cc->disas_set_info = cpu_sparc_disas_set_info;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_num_core_regs = 86;