omap4: l2x0: Enable early BRESP bit

The AXI protocol specifies that the write response can only
be sent back to an AXI master when the last write data has been
accepted. This optimization enables the PL310 to send the write
response of certain write transactions as soon as the store buffer
accepts the write address. This behavior is not compatible with
the AXI protocol and is disabled by default. You enable this
optimization by setting the Early BRESP Enable bit in the
Auxiliary Control Register (bit [30]).

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 2006da10f5f5258d6ad4879e3eece4b658240afa..e7a9b7f13b525d59acce1b337c4dd731d2e59955 100644 (file)
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -82,7 +82,8 @@ static int __init omap_l2_cache_init(void)
                aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
                        (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
                        (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
-                       (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT));
+                       (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+                       (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
        }
        if (omap_rev() != OMAP4430_REV_ES1_0)
                omap_smc1(0x109, aux_ctrl);