dt-bindings: ti-serdes-mux: Add defines for J7200 SoC

There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
select upto 4 different IPs. Define all the possible functions.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Cc: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20200930122032.23481-2-rogerq@ti.com

diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 146d0685a9251a47c698057031a973712f2ae47d..9047ec6bd3cf82dceffd67e3d2d2bfc318e6a55b 100644 (file)
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -68,4 +68,26 @@
 #define J721E_SERDES4_LANE3_QSGMII_LANE8       0x2
 #define J721E_SERDES4_LANE3_IP4_UNUSED         0x3
 
+/* J7200 */
+
+#define J7200_SERDES0_LANE0_QSGMII_LANE3       0x0
+#define J7200_SERDES0_LANE0_PCIE1_LANE0                0x1
+#define J7200_SERDES0_LANE0_IP3_UNUSED         0x2
+#define J7200_SERDES0_LANE0_IP4_UNUSED         0x3
+
+#define J7200_SERDES0_LANE1_QSGMII_LANE4       0x0
+#define J7200_SERDES0_LANE1_PCIE1_LANE1                0x1
+#define J7200_SERDES0_LANE1_IP3_UNUSED         0x2
+#define J7200_SERDES0_LANE1_IP4_UNUSED         0x3
+
+#define J7200_SERDES0_LANE2_QSGMII_LANE1       0x0
+#define J7200_SERDES0_LANE2_PCIE1_LANE2                0x1
+#define J7200_SERDES0_LANE2_IP3_UNUSED         0x2
+#define J7200_SERDES0_LANE2_IP4_UNUSED         0x3
+
+#define J7200_SERDES0_LANE3_QSGMII_LANE2       0x0
+#define J7200_SERDES0_LANE3_PCIE1_LANE3                0x1
+#define J7200_SERDES0_LANE3_USB                        0x2
+#define J7200_SERDES0_LANE3_IP4_UNUSED         0x3
+
 #endif /* _DT_BINDINGS_MUX_TI_SERDES */