target-tricore: add add.f/sub.f instructions

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1457708597-3025-4-git-send-email-kbastian@mail.uni-paderborn.de>

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 7c79c9c6dfced234bf8b2e591e17cf935b857c0c..747d89752536acdbef4e876bfc5c66a81c567b09 100644 (file)
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -47,7 +47,7 @@ static inline bool f_is_denormal(float32 arg)
     return float32_is_zero_or_denormal(arg) && !float32_is_zero(arg);
 }
 
-static inline void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
+static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
 {
     uint8_t some_excp = 0;
     set_float_exception_flags(0, &env->fp_status);
@@ -79,3 +79,30 @@ static inline void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
 
     env->FPU_FS = some_excp;
 }
+
+#define FADD_SUB(op)                                                           \
+uint32_t helper_f##op(CPUTriCoreState *env, uint32_t r1, uint32_t r2)          \
+{                                                                              \
+    float32 arg1 = make_float32(r1);                                           \
+    float32 arg2 = make_float32(r2);                                           \
+    uint32_t flags;                                                            \
+    float32 f_result;                                                          \
+                                                                               \
+    f_result = float32_##op(arg2, arg1, &env->fp_status);                      \
+    flags = f_get_excp_flags(env);                                             \
+    if (flags) {                                                               \
+        /* If the output is a NaN, but the inputs aren't,                      \
+           we return a unique value.  */                                       \
+        if ((flags & float_flag_invalid)                                       \
+            && !float32_is_any_nan(arg1)                                       \
+            && !float32_is_any_nan(arg2)) {                                    \
+            f_result = ADD_NAN;                                                \
+        }                                                                      \
+        f_update_psw_flags(env, flags);                                        \
+    } else {                                                                   \
+        env->FPU_FS = 0;                                                       \
+    }                                                                          \
+    return (uint32_t)f_result;                                                 \
+}
+FADD_SUB(add)
+FADD_SUB(sub)

diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 2c8ed7894048d7089130a1795f52312c05a5d0f5..2f4a2bb63945caefdb839e5f989eca6374e635ad 100644 (file)
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -105,6 +105,8 @@ DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
 /* float */
 DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32)
 DEF_HELPER_1(unpack, i64, i32)
+DEF_HELPER_3(fadd, i32, env, i32, i32)
+DEF_HELPER_3(fsub, i32, env, i32, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index bccdcc3ecfab318dfd2f5f26bcb887c926155474..c4c7717bdbca9eff5cd9f75c6900913b37e63ee0 100644 (file)
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7061,6 +7061,12 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
         gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
                         cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RRR_ADD_F:
+        gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+        break;
+    case OPC2_32_RRR_SUB_F:
+        gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }