}
imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+
+ imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
+ imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
}
#endif /* ifdef CONFIG_SOC_IMX31 */
#include <linux/module.h>
+#include <linux/io.h>
#include <mach/hardware.h>
unsigned int __mxc_cpu_type;
pr_info("CPU identified as %s, silicon rev %d.%d\n",
cpu, (srev >> 4) & 0xf, srev & 0xf);
}
+
+void __init imx_set_aips(void __iomem *base)
+{
+ unsigned int reg;
+/*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ __raw_writel(0x77777777, base + 0x0);
+ __raw_writel(0x77777777, base + 0x4);
+
+/*
+ * Set all OPACRx to be non-bufferable, to not require
+ * supervisor privilege level for access, allow for
+ * write access and untrusted master access.
+ */
+ __raw_writel(0x0, base + 0x40);
+ __raw_writel(0x0, base + 0x44);
+ __raw_writel(0x0, base + 0x48);
+ __raw_writel(0x0, base + 0x4C);
+ reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+ __raw_writel(reg, base + 0x50);
+}
extern void mxc_arch_reset_init(void __iomem *);
extern int mx53_revision(void);
extern int mx53_display_revision(void);
+extern void imx_set_aips(void __iomem *);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */