]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/commitdiff
arm64: dts: qcom: Add msm8916 CoreSight components
authorIvan T. Ivanov <ivan.ivanov@linaro.org>
Wed, 29 Apr 2015 07:53:41 +0000 (10:53 +0300)
committerKleber Sacilotto de Souza <kleber.souza@canonical.com>
Fri, 13 Apr 2018 14:00:08 +0000 (16:00 +0200)
Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi [new file with mode: 0644]

diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
new file mode 100644 (file)
index 0000000..c008dc7
--- /dev/null
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+
+       tpiu@820000 {
+               compatible = "arm,coresight-tpiu", "arm,primecell";
+               reg = <0x820000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               port {
+                       tpiu_in: endpoint {
+                               slave-mode;
+                               remote-endpoint = <&replicator_out1>;
+                       };
+               };
+       };
+
+       funnel@821000 {
+               compatible = "arm,coresight-funnel", "arm,primecell";
+               reg = <0x821000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       /*
+                        * Not described input ports:
+                        * 0 - connected to Resource and Power Manger CPU ETM
+                        * 1 - not-connected
+                        * 2 - connected to Modem CPU ETM
+                        * 3 - not-connected
+                        * 5 - not-connected
+                        * 6 - connected trought funnel to Wireless CPU ETM
+                        * 7 - connected to STM component
+                        */
+                       port@4 {
+                               reg = <4>;
+                               funnel0_in4: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&funnel1_out>;
+                               };
+                       };
+                       port@8 {
+                               reg = <0>;
+                               funnel0_out: endpoint {
+                                       remote-endpoint = <&etf_in>;
+                               };
+                       };
+               };
+       };
+
+       replicator@824000 {
+               compatible = "qcom,coresight-replicator1x", "arm,primecell";
+               reg = <0x824000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               replicator_out0: endpoint {
+                                       remote-endpoint = <&etr_in>;
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+                               replicator_out1: endpoint {
+                                       remote-endpoint = <&tpiu_in>;
+                               };
+                       };
+                       port@2 {
+                               reg = <0>;
+                               replicator_in: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&etf_out>;
+                               };
+                       };
+               };
+       };
+
+       etf@825000 {
+               compatible = "arm,coresight-tmc", "arm,primecell";
+               reg = <0x825000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               etf_out: endpoint {
+                                       remote-endpoint = <&replicator_in>;
+                               };
+                       };
+                       port@1 {
+                               reg = <0>;
+                               etf_in: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&funnel0_out>;
+                               };
+                       };
+               };
+       };
+
+       etr@826000 {
+               compatible = "arm,coresight-tmc", "arm,primecell";
+               reg = <0x826000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               port {
+                       etr_in: endpoint {
+                               slave-mode;
+                               remote-endpoint = <&replicator_out0>;
+                       };
+               };
+       };
+
+       funnel@841000 { /* APSS funnel only 4 inputs are used */
+               compatible = "arm,coresight-funnel", "arm,primecell";
+               reg = <0x841000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               funnel1_in0: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&etm0_out>;
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+                               funnel1_in1: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&etm1_out>;
+                               };
+                       };
+                       port@2 {
+                               reg = <2>;
+                               funnel1_in2: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&etm2_out>;
+                               };
+                       };
+                       port@3 {
+                               reg = <3>;
+                               funnel1_in3: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&etm3_out>;
+                               };
+                       };
+                       port@4 {
+                               reg = <0>;
+                               funnel1_out: endpoint {
+                                       remote-endpoint = <&funnel0_in4>;
+                               };
+                       };
+               };
+       };
+
+       etm@85c000 {
+               compatible = "arm,coresight-etm4x", "arm,primecell";
+               reg = <0x85c000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               cpu = <&CPU0>;
+
+               port {
+                       etm0_out: endpoint {
+                               remote-endpoint = <&funnel1_in0>;
+                       };
+               };
+       };
+
+       etm@85d000 {
+               compatible = "arm,coresight-etm4x", "arm,primecell";
+               reg = <0x85d000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               cpu = <&CPU1>;
+
+               port {
+                       etm1_out: endpoint {
+                               remote-endpoint = <&funnel1_in1>;
+                       };
+               };
+       };
+
+       etm@85e000 {
+               compatible = "arm,coresight-etm4x", "arm,primecell";
+               reg = <0x85e000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               cpu = <&CPU2>;
+
+               port {
+                       etm2_out: endpoint {
+                               remote-endpoint = <&funnel1_in2>;
+                       };
+               };
+       };
+
+       etm@85f000 {
+               compatible = "arm,coresight-etm4x", "arm,primecell";
+               reg = <0x85f000 0x1000>;
+
+               clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+               clock-names = "apb_pclk", "atclk";
+
+               cpu = <&CPU3>;
+
+               port {
+                       etm3_out: endpoint {
+                               remote-endpoint = <&funnel1_in3>;
+                       };
+               };
+       };
+};