drm/radeon: update line buffer allocation for dce8

We need to allocate line buffer to each display when
setting up the watermarks.  Failure to do so can lead
to a blank screen.  This fixes blank screen problems
on dce8 asics.

Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 582f8e4f36d4372ef86120f871a4f8014589291c..1942571496ea1f8c09803a49f6c9db5b7ad0ccd7 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7367,8 +7367,8 @@ static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
                                   struct radeon_crtc *radeon_crtc,
                                   struct drm_display_mode *mode)
 {
-       u32 tmp;
-
+       u32 tmp, buffer_alloc, i;
+       u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
        /*
         * Line Buffer Setup
         * There are 6 line buffers, one for each display controllers.
@@ -7378,22 +7378,37 @@ static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
         * them using the stereo blender.
         */
        if (radeon_crtc->base.enabled && mode) {
-               if (mode->crtc_hdisplay < 1920)
+               if (mode->crtc_hdisplay < 1920) {
                        tmp = 1;
-               else if (mode->crtc_hdisplay < 2560)
+                       buffer_alloc = 2;
+               } else if (mode->crtc_hdisplay < 2560) {
                        tmp = 2;
-               else if (mode->crtc_hdisplay < 4096)
+                       buffer_alloc = 2;
+               } else if (mode->crtc_hdisplay < 4096) {
                        tmp = 0;
-               else {
+                       buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
+               } else {
                        DRM_DEBUG_KMS("Mode too big for LB!\n");
                        tmp = 0;
+                       buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
                }
-       } else
+       } else {
                tmp = 1;
+               buffer_alloc = 0;
+       }
 
        WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
               LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
 
+       WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
+              DMIF_BUFFERS_ALLOCATED(buffer_alloc));
+       for (i = 0; i < rdev->usec_timeout; i++) {
+               if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
+                   DMIF_BUFFERS_ALLOCATED_COMPLETED)
+                       break;
+               udelay(1);
+       }
+
        if (radeon_crtc->base.enabled && mode) {
                switch (tmp) {
                case 0:

diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 6a92f491cb91e35a9729fc82d8557cf71cf03b3d..203d2a09a1f55a43768fccce195ac85115efc7f0 100644 (file)
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -393,6 +393,10 @@
 
 #define DMIF_ADDR_CALC                                 0xC00
 
+#define        PIPE0_DMIF_BUFFER_CONTROL                         0x0ca0
+#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
+#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
+
 #define        SRBM_GFX_CNTL                                   0xE44
 #define                PIPEID(x)                                       ((x) << 0)
 #define                MEID(x)                                         ((x) << 2)