Merge branch 'for-next/rng' into for-next/core

* for-next/rng: (2 commits)
  arm64: Use v8.5-RNG entropy for KASLR seed
  ...

diff --cc Documentation/arm64/cpu-feature-registers.rst
Simple merge

diff --cc Documentation/arm64/elf_hwcaps.rst
index 4fafc57d8e737fa2e72ca68fcf34c517f2aca62c,276a33414b229b78f070061ec085ee9872bcc66e..7dfb97dfe416058f20ef3863c9185d9a071f46ec
--- 1/Documentation/arm64/elf_hwcaps.rst
--- 2/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@@ -204,34 -204,11 +204,38 @@@ HWCAP2_FRIN
  
      Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
  
 -
 +HWCAP2_SVEI8MM
 +
 +    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
 +
 +HWCAP2_SVEF32MM
 +
 +    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
 +
 +HWCAP2_SVEF64MM
 +
 +    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
 +
 +HWCAP2_SVEBF16
 +
 +    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
 +
 +HWCAP2_I8MM
 +
 +    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
 +
 +HWCAP2_BF16
 +
 +    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.
 +
 +HWCAP2_DGH
 +
 +    Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.
 +
+ HWCAP2_RNG
+ 
+     Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
+ 
  4. Unused AT_HWCAP bits
  -----------------------
  

diff --cc arch/arm64/Kconfig
index 688c5152befd975e73a5f121808e9f160ef098cc,835f8158220eb122a2f7a45a20b865b9dec41112..0ef172afc30179d4a92604227365e0b0afbb991c
--- 1/arch/arm64/Kconfig
--- 2/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@@ -1516,18 -1486,14 +1516,26 @@@ endmen
  
  menu "ARMv8.5 architectural features"
  
 +config ARM64_E0PD
 +      bool "Enable support for E0PD"
 +      default y
 +      help
 +        E0PD (part of the ARMv8.5 extensions) allows us to ensure
 +        that EL0 accesses made via TTBR1 always fault in constant time,
 +        providing similar benefits to KASLR as those provided by KPTI, but
 +        with lower overhead and without disrupting legitimate access to
 +        kernel memory such as SPE.
 +
 +        This option enables E0PD for TTBR1 where available.
 +
+ config ARCH_RANDOM
+       bool "Enable support for random number generation"
+       default y
+       help
+         Random number generation (part of the ARMv8.5 Extensions)
+         provides a high bandwidth, cryptographically secure
+         hardware random number generator.
+ 
  endmenu
  
  config ARM64_SVE

diff --cc arch/arm64/include/asm/cpucaps.h
index a61c33611e39d7c9f7112fc37b24d4ed6103f666,515f4fbcbf91b0a1b34f09d9cd6f6f2b58ef6a04..865e0253fc1ef3c12e496ef8724aececd7677632
--- 1/arch/arm64/include/asm/cpucaps.h
--- 2/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@@ -55,9 -55,9 +55,10 @@@
  #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM   45
  #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM  46
  #define ARM64_WORKAROUND_1542419              47
 -#define ARM64_WORKAROUND_1319367              48
 -#define ARM64_HAS_RNG                         49
 +#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE  48
 +#define ARM64_HAS_E0PD                                49
++#define ARM64_HAS_RNG                         50
  
--#define ARM64_NCAPS                           50
++#define ARM64_NCAPS                           51
  
  #endif /* __ASM_CPUCAPS_H */

diff --cc arch/arm64/include/asm/hwcap.h
index fcb390ea29ea329eb54e2fb533b18dafe3bb5a6e,fa186480e805c117ff4e6ad1ed87a79f821b3e03..0f00265248b5c2d67fab6b9bae98f47dfab8d665
--- 1/arch/arm64/include/asm/hwcap.h
--- 2/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@@ -86,13 -86,7 +86,14 @@@
  #define KERNEL_HWCAP_SVESM4           __khwcap2_feature(SVESM4)
  #define KERNEL_HWCAP_FLAGM2           __khwcap2_feature(FLAGM2)
  #define KERNEL_HWCAP_FRINT            __khwcap2_feature(FRINT)
- #define KERNEL_HWCAP_DGH              __khwcap2_feature(DGH)
 +#define KERNEL_HWCAP_SVEI8MM          __khwcap2_feature(SVEI8MM)
 +#define KERNEL_HWCAP_SVEF32MM         __khwcap2_feature(SVEF32MM)
 +#define KERNEL_HWCAP_SVEF64MM         __khwcap2_feature(SVEF64MM)
 +#define KERNEL_HWCAP_SVEBF16          __khwcap2_feature(SVEBF16)
 +#define KERNEL_HWCAP_I8MM             __khwcap2_feature(I8MM)
 +#define KERNEL_HWCAP_BF16             __khwcap2_feature(BF16)
++#define KERNEL_HWCAP_DGH              __khwcap2_feature(DGH)
+ #define KERNEL_HWCAP_RNG              __khwcap2_feature(RNG)
  
  /*
   * This yields a mask that user programs can use to figure out what

diff --cc arch/arm64/include/asm/sysreg.h
index a2d3271b64bd92818512a82af98252fb54eb24ce,5e718f279469bab5e4572e8c83ef1a3a848bd8b2..b91570ff9db14c199cf9d6ea4fdbc6cde4f8ca12
--- 1/arch/arm64/include/asm/sysreg.h
--- 2/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@@ -539,19 -541,8 +542,20 @@@
                         SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
                         ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
  
 +/* MAIR_ELx memory attributes (used by Linux) */
 +#define MAIR_ATTR_DEVICE_nGnRnE               UL(0x00)
 +#define MAIR_ATTR_DEVICE_nGnRE                UL(0x04)
 +#define MAIR_ATTR_DEVICE_GRE          UL(0x0c)
 +#define MAIR_ATTR_NORMAL_NC           UL(0x44)
 +#define MAIR_ATTR_NORMAL_WT           UL(0xbb)
 +#define MAIR_ATTR_NORMAL              UL(0xff)
 +#define MAIR_ATTR_MASK                        UL(0xff)
 +
 +/* Position the attr at the correct index */
 +#define MAIR_ATTRIDX(attr, idx)               ((attr) << ((idx) * 8))
 +
  /* id_aa64isar0 */
+ #define ID_AA64ISAR0_RNDR_SHIFT               60
  #define ID_AA64ISAR0_TS_SHIFT         52
  #define ID_AA64ISAR0_FHM_SHIFT                48
  #define ID_AA64ISAR0_DP_SHIFT         44

diff --cc arch/arm64/include/uapi/asm/hwcap.h
index e6dad592470302c99b0649298729f00e5a0739df,f192ac33fc76b978f3f1dd8377d4f8d5a5e41a98..7752d93bb50fa486d8e6df27049775e1d61572e8
--- 1/arch/arm64/include/uapi/asm/hwcap.h
--- 2/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@@ -65,12 -65,6 +65,13 @@@
  #define HWCAP2_SVESM4         (1 << 6)
  #define HWCAP2_FLAGM2         (1 << 7)
  #define HWCAP2_FRINT          (1 << 8)
 -#define HWCAP2_RNG            (1 << 9)
 +#define HWCAP2_SVEI8MM                (1 << 9)
 +#define HWCAP2_SVEF32MM               (1 << 10)
 +#define HWCAP2_SVEF64MM               (1 << 11)
 +#define HWCAP2_SVEBF16                (1 << 12)
 +#define HWCAP2_I8MM           (1 << 13)
 +#define HWCAP2_BF16           (1 << 14)
 +#define HWCAP2_DGH            (1 << 15)
++#define HWCAP2_RNG            (1 << 16)
  
  #endif /* _UAPI__ASM_HWCAP_H */

diff --cc arch/arm64/kernel/cpufeature.c
index 0619503cfda05146d3631a55419ad0f56758701b,3b94e8047c9eaf62a54c6e9ab6e1ef0ea86895cd..0b6715625cf6232ba15afb6eca44313c9ad33f41
--- 1/arch/arm64/kernel/cpufeature.c
--- 2/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@@ -1646,18 -1568,17 +1647,30 @@@ static const struct arm64_cpu_capabilit
                .min_field_value = 1,
        },
  #endif
 +#ifdef CONFIG_ARM64_E0PD
 +      {
 +              .desc = "E0PD",
 +              .capability = ARM64_HAS_E0PD,
 +              .type = ARM64_CPUCAP_SYSTEM_FEATURE,
 +              .sys_reg = SYS_ID_AA64MMFR2_EL1,
 +              .sign = FTR_UNSIGNED,
 +              .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
 +              .matches = has_cpuid_feature,
 +              .min_field_value = 1,
 +              .cpu_enable = cpu_enable_e0pd,
 +      },
++#endif
+ #ifdef CONFIG_ARCH_RANDOM
+       {
+               .desc = "Random Number Generator",
+               .capability = ARM64_HAS_RNG,
+               .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+               .matches = has_cpuid_feature,
+               .sys_reg = SYS_ID_AA64ISAR0_EL1,
+               .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
+               .sign = FTR_UNSIGNED,
+               .min_field_value = 1,
+       },
  #endif
        {},
  };

diff --cc arch/arm64/kernel/cpuinfo.c
index 9013b224591a677245422dfdb1f85b5c782a83de,3000dd27816f22012453720e70163c747919812e..86136075ae41042ec32bb0b755ef38a7ce06d051
--- 1/arch/arm64/kernel/cpuinfo.c
--- 2/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@@ -84,13 -84,7 +84,14 @@@ static const char *const hwcap_str[] = 
        "svesm4",
        "flagm2",
        "frint",
 +      "svei8mm",
 +      "svef32mm",
 +      "svef64mm",
 +      "svebf16",
 +      "i8mm",
 +      "bf16",
 +      "dgh",
+       "rng",
        NULL
  };