crypto/nx: Initialize 842 high and normal RxFIFO control registers

BugLink: https://bugs.launchpad.net/bugs/1827755
NX increments readOffset by FIFO size in receive FIFO control register
when CRB is read. But the index in RxFIFO has to match with the
corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
may be processing incorrect CRBs and can cause CRB timeout.

VAS FIFO offset is 0 when the receive window is opened during
initialization. When the module is reloaded or in kexec boot, readOffset
in FIFO control register may not match with VAS entry. This patch adds
nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
control register for both high and normal FIFOs.

Signed-off-by: Haren Myneni <haren@us.ibm.com>
[mpe: Fixup uninitialized variable warning]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
(backported from commit 656ecc16e8fc2ab44b3d70e3fcc197a7020d0ca5)
Signed-off-by: Manoj Iyer <manoj.iyer@canonical.com>
Acked-by: Khalid Elmously <khalid.elmously@canonical.com>
Acked-by: Connor Kuehl <connor.kuehl@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>

diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index e2515843b37eb89a06e555bd16ce6e64e85da4c2..20a6c9a0e3f1917fceb8e3804761a00b5c061a5f 100644 (file)
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -207,7 +207,8 @@
 #define OPAL_NPU_TL_SET                                161
 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR           164
 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR           165
-#define OPAL_LAST                              165
+#define        OPAL_NX_COPROC_INIT                     167
+#define OPAL_LAST                              167
 
 #define QUIESCE_HOLD                   1 /* Spin all calls at entry */
 #define QUIESCE_REJECT                 2 /* Fail all calls with OPAL_BUSY */

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 5e3dd3bf76021b347fb84f88b9b12349783aeb33..6cef5bcc5763bdcfd5d79a1453b24a7e5078b0b4 100644 (file)
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -291,6 +291,7 @@ int opal_set_powercap(u32 handle, int token, u32 pcap);
 int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
 int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
 int opal_sensor_group_clear(u32 group_hndl, int token);
+int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
 
 s64 opal_signal_system_reset(s32 cpu);
 s64 opal_quiesce(u64 shutdown_type, s32 cpu);

diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index 5eb1466665a423cdeee4d055440d700af9c331a0..25931305e7941b617f44d8ae2224cd8a5c2ce7a7 100644 (file)
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -326,3 +326,4 @@ OPAL_CALL(opal_npu_spa_clear_cache,         OPAL_NPU_SPA_CLEAR_CACHE);
 OPAL_CALL(opal_npu_tl_set,                     OPAL_NPU_TL_SET);
 OPAL_CALL(opal_pci_get_pbcq_tunnel_bar,                OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
 OPAL_CALL(opal_pci_set_pbcq_tunnel_bar,                OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
+OPAL_CALL(opal_nx_coproc_init,                 OPAL_NX_COPROC_INIT);

diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 4bd365fad70175b320d52797b787415924a3a84b..efd7c0b88839ce1f39c5b8dca2ec6a3d5d29abc3 100644 (file)
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -1043,3 +1043,5 @@ EXPORT_SYMBOL_GPL(opal_write_oppanel_async);
 EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
 EXPORT_SYMBOL_GPL(opal_int_eoi);
 EXPORT_SYMBOL_GPL(opal_error_code);
+/* Export the below symbol for NX compression */
+EXPORT_SYMBOL(opal_nx_coproc_init);

diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
index f2246a5abcf6e0e87cce76cdcad227c78d317537..c48a13c593248067d19dad2a32dea73ea18ac626 100644 (file)
--- a/drivers/crypto/nx/nx-842-powernv.c
+++ b/drivers/crypto/nx/nx-842-powernv.c
@@ -24,6 +24,8 @@
 #include <asm/icswx.h>
 #include <asm/vas.h>
 #include <asm/reg.h>
+#include <asm/opal-api.h>
+#include <asm/opal.h>
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
@@ -753,7 +755,7 @@ static int nx842_open_percpu_txwins(void)
 }
 
 static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
-                                       int vasid)
+                                       int vasid, int *ct)
 {
        struct vas_window *rxwin = NULL;
        struct vas_rx_win_attr rxattr;
@@ -837,6 +839,15 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
        coproc->vas.id = vasid;
        nx842_add_coprocs_list(coproc, chip_id);
 
+       /*
+        * (lpid, pid, tid) combination has to be unique for each
+        * coprocessor instance in the system. So to make it
+        * unique, skiboot uses coprocessor type such as 842 or
+        * GZIP for pid and provides this value to kernel in pid
+        * device-tree property.
+        */
+       *ct = pid;
+
        return 0;
 
 err_out:
@@ -850,6 +861,7 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
        struct device_node *dn;
        int chip_id, vasid, ret = 0;
        int nx_fifo_found = 0;
+       int uninitialized_var(ct);
 
        chip_id = of_get_ibm_chip_id(pn);
        if (chip_id < 0) {
@@ -865,7 +877,7 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
 
        for_each_child_of_node(pn, dn) {
                if (of_device_is_compatible(dn, "ibm,p9-nx-842")) {
-                       ret = vas_cfg_coproc_info(dn, chip_id, vasid);
+                       ret = vas_cfg_coproc_info(dn, chip_id, vasid, &ct);
                        if (ret) {
                                of_node_put(dn);
                                return ret;
@@ -876,9 +888,22 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
 
        if (!nx_fifo_found) {
                pr_err("NX842 FIFO nodes are missing\n");
-               ret = -EINVAL;
+               return -EINVAL;
        }
 
+       /*
+        * Initialize NX instance for both high and normal priority FIFOs.
+        */
+       if (opal_check_token(OPAL_NX_COPROC_INIT)) {
+               ret = opal_nx_coproc_init(chip_id, ct);
+               if (ret) {
+                       pr_err("Failed to initialize NX for chip(%d): %d\n",
+                               chip_id, ret);
+                       ret = opal_error_code(ret);
+               }
+       } else
+               pr_warn("Firmware doesn't support NX initialization\n");
+
        return ret;
 }