net: phy: micrel.c: add rgmii interface delay possibility to ksz9131

The KSZ9131 provides DLL controlled delays on RXC and TXC lines. This
patch makes use of those delays. The information which delays should
be enabled or disabled comes from the interface names, documented in
ethernet-controller.yaml:

rgmii:      Disable RXC and TXC delays
rgmii-id:   Enable RXC and TXC delays
rgmii-txid: Enable only TXC delay, disable RXC delay
rgmii-rxid: Enable onlx RXC delay, disable TXC delay

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 63dedec0433def38409d22df1b8db08ff2954005..2ec19e5540bff612d1e2aaa73b28acf1bb58e313 100644 (file)
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -704,6 +704,50 @@ static int ksz9131_of_load_skew_values(struct phy_device *phydev,
        return phy_write_mmd(phydev, 2, reg, newval);
 }
 
+#define KSZ9131RN_MMD_COMMON_CTRL_REG  2
+#define KSZ9131RN_RXC_DLL_CTRL         76
+#define KSZ9131RN_TXC_DLL_CTRL         77
+#define KSZ9131RN_DLL_CTRL_BYPASS      BIT_MASK(12)
+#define KSZ9131RN_DLL_ENABLE_DELAY     0
+#define KSZ9131RN_DLL_DISABLE_DELAY    BIT(12)
+
+static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
+{
+       u16 rxcdll_val, txcdll_val;
+       int ret;
+
+       switch (phydev->interface) {
+       case PHY_INTERFACE_MODE_RGMII:
+               rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+               txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+               break;
+       case PHY_INTERFACE_MODE_RGMII_ID:
+               rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+               txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+               break;
+       case PHY_INTERFACE_MODE_RGMII_RXID:
+               rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+               txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+               break;
+       case PHY_INTERFACE_MODE_RGMII_TXID:
+               rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
+               txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
+               break;
+       default:
+               return 0;
+       }
+
+       ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+                            KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+                            rxcdll_val);
+       if (ret < 0)
+               return ret;
+
+       return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+                             KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+                             txcdll_val);
+}
+
 static int ksz9131_config_init(struct phy_device *phydev)
 {
        const struct device *dev = &phydev->mdio.dev;
@@ -730,6 +774,12 @@ static int ksz9131_config_init(struct phy_device *phydev)
        if (!of_node)
                return 0;
 
+       if (phy_interface_is_rgmii(phydev)) {
+               ret = ksz9131_config_rgmii_delay(phydev);
+               if (ret < 0)
+                       return ret;
+       }
+
        ret = ksz9131_of_load_skew_values(phydev, of_node,
                                          MII_KSZ9031RN_CLK_PAD_SKEW, 5,
                                          clk_skews, 2);