]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/commitdiff
ARM: tegra: Update sound node clocks in device tree
authorSowjanya Komatineni <skomatineni@nvidia.com>
Tue, 14 Jan 2020 07:24:20 +0000 (23:24 -0800)
committerThierry Reding <treding@nvidia.com>
Fri, 13 Mar 2020 10:25:44 +0000 (11:25 +0100)
clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block but were
previously erroneously provided by the clock and reset controller.

clk_out_1 is dedicated for audio mclk on Tegra30 through Tegra210.

This patch updates device tree sound node to use clk_out_1 from the PMC
provider as mclk and uses assigned-clock properties to specify clock
parents for clk_out_1 and extern1.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/boot/dts/tegra114-dalmore.dts
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
arch/arm/boot/dts/tegra124-apalis.dtsi
arch/arm/boot/dts/tegra124-jetson-tk1.dts
arch/arm/boot/dts/tegra124-nyan.dtsi
arch/arm/boot/dts/tegra124-venice2.dts
arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
arch/arm/boot/dts/tegra30-apalis.dtsi
arch/arm/boot/dts/tegra30-beaver.dts
arch/arm/boot/dts/tegra30-cardhu.dtsi
arch/arm/boot/dts/tegra30-colibri.dtsi

index 97a5c3504bbeb38b0ba496570c28a4ff42ddd4be..d3e032e7d21a0b415974a3e5f1b65816f99dbd77 100644 (file)
 
                clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
                         <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA114_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA114_CLK_EXTERN1>;
        };
 };
index 0462ed2dd8b8db286cb149c25557642cbea86cc2..de499f736bda379a182a7978d6e16819dfce7eb3 100644 (file)
                nvidia,audio-codec = <&sgtl5000>;
                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA124_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA124_CLK_EXTERN1>;
        };
 
        thermal-zones {
index d1e8593ef0d900f8d23d525b02f1ca41a6dfff78..d70a86da4ee4cd63652dbebe820835062b99e470 100644 (file)
                nvidia,audio-codec = <&sgtl5000>;
                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA124_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA124_CLK_EXTERN1>;
        };
 
        thermal-zones {
index 54600ffa7a7450f5330f251bd3e64a1af6c6ff8d..1b567e2d5ce063a543acb5dfcdc26ec7689c048d 100644 (file)
 
                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA124_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA124_CLK_EXTERN1>;
        };
 
        thermal-zones {
index 3b10f475037f77f4d651276396546f08b0df58e0..9b1af50cd4b8b2a77294bd0848e526ac88f83031 100644 (file)
 
                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA124_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
 
+               assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA124_CLK_EXTERN1>;
+
                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
                nvidia,mic-det-gpios =
                                <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
index 7309393bfced1a4f67bed1699a6bae6c1c50d963..8c2ee6e7d6f1abb30941fb512dba688fc846aeac 100644 (file)
 
                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA124_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA124_CLK_EXTERN1>;
        };
 };
 
index 8b7a827d604d8bacdd83fdda18af7644bf37306b..387b17458e228224dc9105cb42d3fbc7ded3f307 100644 (file)
                nvidia,audio-codec = <&sgtl5000>;
                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA30_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA30_CLK_EXTERN1>;
        };
 };
index c18f6f61d76493b2882f8b5ad71489e64f97b635..6648506f3aa488ded7bb22078793e1fadc0c663a 100644 (file)
                nvidia,audio-codec = <&sgtl5000>;
                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA30_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA30_CLK_EXTERN1>;
        };
 };
index a3b0f3555cd243665434a979b461965957ca758a..45ef6002b2257650f35c2f79ecb7c85831124e09 100644 (file)
 
                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA30_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA30_CLK_EXTERN1>;
        };
 };
index 7ce61edd52f5cd28b78879bc85f1ede92e5d0c99..4b4f49a49394b753d8a8a2377eae49bf2f61a75f 100644 (file)
 
                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA30_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA30_CLK_EXTERN1>;
        };
 
        gpio-keys {
index 1f9198bb24ff3f7a0fe7352a090f007dc3153e82..adba554381c7824b805d38910c2569b1a91f2eaa 100644 (file)
                nvidia,audio-codec = <&sgtl5000>;
                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
-                        <&tegra_car TEGRA30_CLK_EXTERN1>;
+                        <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
+
+               assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+                                 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+               assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                                        <&tegra_car TEGRA30_CLK_EXTERN1>;
        };
 };