drm/amd/powerplay: remove setting soc floor voltage before sending pptable

SOC voltage is not able to switch and forced to low 0.8V when running HEVC.
Thus the test failed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index ed928c5d878c8ece26b75227229f3ef3e25f33d1..ad6ce148fb3fde151b92c24f3ca7e3d4afd0a492 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -707,14 +707,7 @@ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
        data->vbios_boot_state.vclock = boot_up_values.ulVClk;
        data->vbios_boot_state.dclock = boot_up_values.ulDClk;
        data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
-       if (0 != boot_up_values.usVddc) {
-               smum_send_msg_to_smc_with_parameter(hwmgr,
-                                       PPSMC_MSG_SetFloorSocVoltage,
-                                       (boot_up_values.usVddc * 4));
-               data->vbios_boot_state.bsoc_vddc_lock = true;
-       } else {
-               data->vbios_boot_state.bsoc_vddc_lock = false;
-       }
+
        smum_send_msg_to_smc_with_parameter(hwmgr,
                        PPSMC_MSG_SetMinDeepSleepDcefclk,
                (uint32_t)(data->vbios_boot_state.dcef_clock / 100));

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 130052a330b301b673504549601f8a375e73c533..72e4f2a556414c84ee43296b1f9319c02103af3f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -203,7 +203,6 @@ struct vega20_dpmlevel_enable_mask {
 };
 
 struct vega20_vbios_boot_state {
-       bool        bsoc_vddc_lock;
        uint8_t     uc_cooling_id;
        uint16_t    vddc;
        uint16_t    vddci;