ARM: 8843/1: use unified assembler in headers

Use unified assembler syntax (UAL) in headers. Divided syntax is
considered deprecated. This will also allow to build the kernel
using LLVM's integrated assembler.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 28a48e0d4cca04f65b8bc90179c8daf5a3632397..b59921a560da3ea0fb72baa5194a1aced4239c6e 100644 (file)
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -376,9 +376,9 @@ THUMB(      orr     \reg , \reg , #PSR_T_BIT        )
        .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
 9999:
        .if     \inc == 1
-       \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
+       \instr\()b\t\cond\().w \reg, [\ptr, #\off]
        .elseif \inc == 4
-       \instr\cond\()\t\().w \reg, [\ptr, #\off]
+       \instr\t\cond\().w \reg, [\ptr, #\off]
        .else
        .error  "Unsupported inc macro argument"
        .endif
@@ -417,9 +417,9 @@ THUMB(      orr     \reg , \reg , #PSR_T_BIT        )
        .rept   \rept
 9999:
        .if     \inc == 1
-       \instr\cond\()b\()\t \reg, [\ptr], #\inc
+       \instr\()b\t\cond \reg, [\ptr], #\inc
        .elseif \inc == 4
-       \instr\cond\()\t \reg, [\ptr], #\inc
+       \instr\t\cond \reg, [\ptr], #\inc
        .else
        .error  "Unsupported inc macro argument"
        .endif
@@ -460,7 +460,7 @@ THUMB(      orr     \reg , \reg , #PSR_T_BIT        )
        .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
 #ifndef CONFIG_CPU_USE_DOMAINS
        adds    \tmp, \addr, #\size - 1
-       sbcccs  \tmp, \tmp, \limit
+       sbcscc  \tmp, \tmp, \limit
        bcs     \bad
 #ifdef CONFIG_CPU_SPECTRE
        movcs   \addr, #0
@@ -474,7 +474,7 @@ THUMB(      orr     \reg , \reg , #PSR_T_BIT        )
        sub     \tmp, \limit, #1
        subs    \tmp, \tmp, \addr       @ tmp = limit - 1 - addr
        addhs   \tmp, \tmp, #1          @ if (tmp >= 0) {
-       subhss  \tmp, \tmp, \size       @ tmp = limit - (addr + size) }
+       subshs  \tmp, \tmp, \size       @ tmp = limit - (addr + size) }
        movlo   \addr, #0               @ if (tmp < 0) addr = NULL
        csdb
 #endif

diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index ef5dfedacd8d642bdfe27147e37bdec0a6f055bb..628c336e8e3b20c5918f58d9d8f5139b10723953 100644 (file)
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -29,13 +29,13 @@
        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
        ldr     \tmp, [\tmp, #0]
        tst     \tmp, #HWCAP_VFPD32
-       ldcnel  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+       ldclne  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
        addeq   \base, \base, #32*4                 @ step over unused register space
 #else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
        cmp     \tmp, #2                            @ 32 x 64bit registers?
-       ldceql  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
+       ldcleq  p11, cr0, [\base],#32*4             @ FLDMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
 #endif
 #endif
@@ -53,13 +53,13 @@
        ldr     \tmp, =elf_hwcap                    @ may not have MVFR regs
        ldr     \tmp, [\tmp, #0]
        tst     \tmp, #HWCAP_VFPD32
-       stcnel  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+       stclne  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
        addeq   \base, \base, #32*4                 @ step over unused register space
 #else
        VFPFMRX \tmp, MVFR0                         @ Media and VFP Feature Register 0
        and     \tmp, \tmp, #MVFR0_A_SIMD_MASK      @ A_SIMD field
        cmp     \tmp, #2                            @ 32 x 64bit registers?
-       stceql  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
+       stcleq  p11, cr0, [\base],#32*4             @ FSTMIAD \base!, {d16-d31}
        addne   \base, \base, #32*4                 @ step over unused register space
 #endif
 #endif

diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 93cddab73072cc716b07c0353ec79bdbaec3757a..95bd359912889a5d31ceaefeaefb7597deaf5c14 100644 (file)
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -7,7 +7,7 @@
 ENTRY( \name           )
 UNWIND(        .fnstart        )
        ands    ip, r1, #3
-       strneb  r1, [ip]                @ assert word-aligned
+       strbne  r1, [ip]                @ assert word-aligned
        mov     r2, #1
        and     r3, r0, #31             @ Get bit offset
        mov     r0, r0, lsr #5
@@ -32,7 +32,7 @@ ENDPROC(\name         )
 ENTRY( \name           )
 UNWIND(        .fnstart        )
        ands    ip, r1, #3
-       strneb  r1, [ip]                @ assert word-aligned
+       strbne  r1, [ip]                @ assert word-aligned
        mov     r2, #1
        and     r3, r0, #31             @ Get bit offset
        mov     r0, r0, lsr #5
@@ -62,7 +62,7 @@ ENDPROC(\name         )
 ENTRY( \name           )
 UNWIND(        .fnstart        )
        ands    ip, r1, #3
-       strneb  r1, [ip]                @ assert word-aligned
+       strbne  r1, [ip]                @ assert word-aligned
        and     r2, r0, #31
        mov     r0, r0, lsr #5
        mov     r3, #1
@@ -89,7 +89,7 @@ ENDPROC(\name         )
 ENTRY( \name           )
 UNWIND(        .fnstart        )
        ands    ip, r1, #3
-       strneb  r1, [ip]                @ assert word-aligned
+       strbne  r1, [ip]                @ assert word-aligned
        and     r3, r0, #31
        mov     r0, r0, lsr #5
        save_and_disable_irqs ip