drm/i915: fix to setup display reference clock control on Ironlake

For new stepping of PCH, the display reference clock
is fully under driver's control. This one trys to setup
all needed reference clock for different outputs. Older
stepping of PCH chipset should be ignoring this.

This fixes output failure issue on newer PCH which requires
driver to take control of reference clock enabling.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4813586d92ccd6cd81fce0976431fefd20e9742..cd0ffa015c27cda1fad42e21d2d21ed00a0956df 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2158,11 +2158,11 @@
 #define  DREF_CPU_SOURCE_OUTPUT_MASK           (3<<13)
 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
-#define  DREF_SSC_SOURCE_MASK                  (2<<11)
+#define  DREF_SSC_SOURCE_MASK                  (3<<11)
 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
 #define  DREF_NONSPREAD_CK505_ENABLE           (1<<9)
 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
-#define  DREF_NONSPREAD_SOURCE_MASK            (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK            (3<<9)
 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 123cce1ae47012689ce1019a16d90b7151daf462..db4c38700951e787002943150b0e2b6230e8eab2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2814,6 +2814,46 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                                  link_bw, &m_n);
        }
 
+       /* Ironlake: try to setup display ref clock before DPLL
+        * enabling. This is only under driver's control after
+        * PCH B stepping, previous chipset stepping should be
+        * ignoring this setting.
+        */
+       if (IS_IGDNG(dev)) {
+               temp = I915_READ(PCH_DREF_CONTROL);
+               /* Always enable nonspread source */
+               temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+               temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+               I915_WRITE(PCH_DREF_CONTROL, temp);
+               POSTING_READ(PCH_DREF_CONTROL);
+
+               temp &= ~DREF_SSC_SOURCE_MASK;
+               temp |= DREF_SSC_SOURCE_ENABLE;
+               I915_WRITE(PCH_DREF_CONTROL, temp);
+               POSTING_READ(PCH_DREF_CONTROL);
+
+               udelay(200);
+
+               if (is_edp) {
+                       if (dev_priv->lvds_use_ssc) {
+                               temp |= DREF_SSC1_ENABLE;
+                               I915_WRITE(PCH_DREF_CONTROL, temp);
+                               POSTING_READ(PCH_DREF_CONTROL);
+
+                               udelay(200);
+
+                               temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+                               temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+                               I915_WRITE(PCH_DREF_CONTROL, temp);
+                               POSTING_READ(PCH_DREF_CONTROL);
+                       } else {
+                               temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+                               I915_WRITE(PCH_DREF_CONTROL, temp);
+                               POSTING_READ(PCH_DREF_CONTROL);
+                       }
+               }
+       }
+
        if (IS_IGD(dev)) {
                fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
                if (has_reduced_clock)