The v7_invalidate_l1 was used for the L1 cache that come out from reset
in a undefined state. This is no need for Cortex-A15. We do it for A9
only.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
.section ".text.head", "ax"
ENTRY(tegra_secondary_startup)
- bl v7_invalidate_l1
+ check_cpu_part_num 0xc09, r8, r9
+ bleq v7_invalidate_l1
b secondary_startup
ENDPROC(tegra_secondary_startup)
* re-enabling sdram.
*
* r6: SoC ID
+ * r8: CPU part number
*/
ENTRY(tegra_resume)
- bl v7_invalidate_l1
+ check_cpu_part_num 0xc09, r8, r9
+ bleq v7_invalidate_l1
cpu_id r0
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
str r1, [r2]
1:
- check_cpu_part_num 0xc09, r8, r9
+ mov32 r9, 0xc09
+ cmp r8, r9
bne not_ca9
#ifdef CONFIG_HAVE_ARM_SCU
/* enable SCU */