Extend TB flags to 64 bits (Alexander Graf).

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3198 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/cpu-exec.c b/cpu-exec.c
index 2d08626db161684854941d58aba37ea76b8263d0..3395059662cc1705fbb3d625e35402940c4e4fb6 100644 (file)
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -77,7 +77,7 @@ void cpu_resume_from_signal(CPUState *env1, void *puc)
 
 static TranslationBlock *tb_find_slow(target_ulong pc,
                                       target_ulong cs_base,
-                                      unsigned int flags)
+                                      uint64_t flags)
 {
     TranslationBlock *tb, **ptb1;
     int code_gen_size;
@@ -155,7 +155,7 @@ static inline TranslationBlock *tb_find_fast(void)
 {
     TranslationBlock *tb;
     target_ulong cs_base, pc;
-    unsigned int flags;
+    uint64_t flags;
 
     /* we record a subset of the CPU state. It will
        always be the same before a given translated block

diff --git a/exec-all.h b/exec-all.h
index ca59597422406a8582f657168626ce52f0d1b71a..f58aea53453e546af1b7b64b835d92fac1c77f55 100644 (file)
--- a/exec-all.h
+++ b/exec-all.h
@@ -171,7 +171,7 @@ static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
 typedef struct TranslationBlock {
     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
     target_ulong cs_base; /* CS base for this block */
-    unsigned int flags; /* flags defining in which context the code was generated */
+    uint64_t flags; /* flags defining in which context the code was generated */
     uint16_t size;      /* size of target code for this block (1 <=
                            size <= TARGET_PAGE_SIZE) */
     uint16_t cflags;    /* compile flags */

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 35ba6319cc2fedc9a0712a5cd29e96b81dfc93dd..028cdac9ada48bd6acff058be641cd443f7dfbb8 100644 (file)
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -95,7 +95,7 @@ typedef struct DisasContext {
     int singlestep_enabled; /* "hardware" single step enabled */
     int jmp_opt; /* use direct block chaining for direct jumps */
     int mem_index; /* select memory access functions */
-    int flags; /* all execution flags */
+    uint64_t flags; /* all execution flags */
     struct TranslationBlock *tb;
     int popl_esp_hack; /* for correct popl with esp base handling */
     int rip_offset; /* only used in x86_64, but left for simplicity */
@@ -6462,7 +6462,8 @@ static inline int gen_intermediate_code_internal(CPUState *env,
     DisasContext dc1, *dc = &dc1;
     target_ulong pc_ptr;
     uint16_t *gen_opc_end;
-    int flags, j, lj, cflags;
+    int j, lj, cflags;
+    uint64_t flags;
     target_ulong pc_start;
     target_ulong cs_base;
 

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8e6fe0e208fa05c7a744f87b39b8494f06067729..ddffc0f15db6a0916a383de601c71af536d467ac 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -6403,7 +6403,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
     ctx.tb = tb;
     ctx.bstate = BS_NONE;
     /* Restore delay slot state from the tb context.  */
-    ctx.hflags = tb->flags;
+    ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
     restore_cpu_state(env, &ctx);
 #if defined(CONFIG_USER_ONLY)
     ctx.mem_idx = 0;